Semiconductor devices and methods of making the same

• US 10,490,488 B2
• Filed: 01/15/2018
• Issued: 11/26/2019
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Arbuthnot, Roger M., St. Germain, Stephen
• Primary Examiner(s): Trinh, Hoa B
• Application Number:
  US15/871,414
• Publication Number:
  US 20180138109A1
• Time in Patent Office: 680 Days
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/04026 Bonding areas specifically adapted for layer connectors
• CPC Class Codes: H01L 2224/04034 Bonding areas specifically adapted for strap connectors
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/26175 Flow barriers
• CPC Class Codes: H01L 2224/291 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/32258 the layer connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 2224/33181 On opposite sides of the body
• CPC Class Codes: H01L 2224/37011 comprising apertures or cavities
• CPC Class Codes: H01L 2224/37012 Cross-sectional shape
• CPC Class Codes: H01L 2224/37099 Material
• CPC Class Codes: H01L 2224/40245 the item being metallic
• CPC Class Codes: H01L 2224/40499 : Material of the auxiliary connecting means
• CPC Class Codes: H01L 2224/4103 : Connectors having different sizes
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48247 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73221 : Strap and wire connectors
• CPC Class Codes: H01L 2224/73263 : Layer and strap connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83192 : wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/83801 : Soldering or alloying
• CPC Class Codes: H01L 2224/83815 : Reflow soldering
• CPC Class Codes: H01L 2224/84385 : Shape, e.g. interlocking features
• CPC Class Codes: H01L 2224/84801 : Soldering or alloying
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/492 : Bases or plates or solder therefor
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49513 : having bonding material between chip and die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/37 : of an individual strap connector
• CPC Class Codes: H01L 24/40 : of an individual strap connector
• CPC Class Codes: H01L 24/41 : of a plurality of strap connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/67 : of a plurality of connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/84 : using a strap connector
• CPC Class Codes: H01L 24/89 : using at least one connector not provided for in any of the groups H01L24/81 - H01L24/86
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

In one embodiment, methods for making semiconductor devices are disclosed.

Claims

1. A method for making a semiconductor device, the method comprising:

providing a conductive substrate, the conductive substrate comprising one or more elevated regions on a first side of the conductive substrate, wherein each of the one or more elevated regions comprises each of one or more planar surfaces on the first side of the conductive substrate;

disposing a solder paste between at least one of the one or more planar surfaces on the one or more elevated regions on the conductive substrate and one or more contact pads of a semiconductor die such that each of the one or more contact pads has two or more linear edges that are each laterally aligned and parallel with at least one edge of the one or more planar surfaces on the one or more elevated regions; and

reflowing the solder paste to solder at least a portion of the elevated regions to the contact pads.

2. The method of claim 1, wherein disposing the solder paste between at least one of the one or more planar surfaces on the one or more elevated regions on the conductive substrate and the one or more contact pads of the semiconductor die comprises disposing the solder paste between two or more planar surfaces of the one or more planar surfaces on the one or more elevated regions on the conductive substrate and the one or more contact pads.

3. The method of claim 1, wherein a number of the elevated regions of the one or more elevated regions on the first side of the conductive substrate is greater than a number of the elevated regions of the one or more elevated regions soldered to the one or more contact pads of the semiconductor die.

4. The method of claim 1, wherein a number of the elevated regions of the one or more elevated regions on the first side of the conductive substrate is at least 10.

5. The method of claim 1, wherein a number of the elevated regions of the one or more elevated regions on the first side of the conductive substrate is at least two, and wherein at least a portion of the elevated regions of the one or more elevated regions on the first side of the conductive substrate have different sizes.

6. The method of claim 1, wherein a number of the elevated regions of the one or more elevated regions on the first side of the conductive substrate is at least two, and wherein the elevated regions of the one or more elevated regions are evenly spaced along a first direction.

7. The method of claim 1, wherein providing the conductive substrate comprises providing a lead frame comprising the conductive substrate electrically coupled to a first lead.

8. The method of claim 1, wherein the one or more elevated regions on the first side of the conductive substrate are arranged in a grid having rows and columns, each of the rows having the same number of elevated regions and each of the columns having the same number of elevated regions.

9. The method of claim 1, wherein the semiconductor die is a metal-oxide field-effect transistor (MOSFET).

10. A method for making a semiconductor device, the method comprising:

providing a conductive substrate, the conductive substrate comprising a first elevated region on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the second elevated region comprises a second planar surface on the first side of the conductive substrate; and

attaching at least the first planar surface of the first elevated region to a first contact pad of a semiconductor die such that the conductive substrate is electrically coupled to the first contact pad, wherein at least a portion of the second planar surface on the second elevated region is not attached to any contact pad of the semiconductor die.

11. The method of claim 10, wherein the first planar surface of the first elevated region has a first corner that is laterally aligned with a first corner of the first contact pad.

12. The method of claim 10, wherein the first planar surface of the first elevated region has different dimensions than the second planar surface of the second elevated region.

13. The method of claim 10, wherein the conductive substrate comprises at least 10 elevated regions.

14. The method of claim 10, wherein the semiconductor die is a metal-oxide field-effect transistor (MOSFET).

15. The method of claim 10, wherein the second planar surface of the second elevated region is not attached to the semiconductor die.

16. The method of claim 10, wherein only a portion of the second planar surface of the second elevated region is attached to the first contact pad of the semiconductor die, and wherein the second planar surface of the second elevated region is electrically coupled to the first contact pad of the semiconductor die.

17. The method of claim 10, wherein the first planar surface comprises a curved edge, and wherein the second planar surface has a polygonal shape.

18. The method of claim 10, wherein a first portion of the second planar surface of the second elevated region is attached to the first contact pad of the semiconductor die, and a second portion of the second planar surface of the second elevated region is attached to a second contact pad of the semiconductor die.

19. The method of claim 10, wherein the second planar surface of the second elevated region is laterally positioned away from a footprint of the semiconductor die.

20. A method for making semiconductor devices, the method comprising:

providing a first conductive substrate, the first conductive substrate comprising one or more elevated regions on a first side of the first conductive substrate, wherein each of the one or more elevated regions of the first conductive substrate comprises a planar surface on the first side of the first conductive substrate;

providing a second conductive substrate, the second conductive substrate comprising one or more elevated regions on a first side of the second conductive substrate, wherein each of the one or more elevated regions of the second conductive substrate comprises a planar surface on the first side of the second conductive substrate, wherein the first conductive substrate has substantially the same structure as the second conductive substrate;

attaching one or more contact pads of a first semiconductor die to at least one of said one or more elevated regions on the first side of the first conductive substrate; and

attaching one or more contact pads of a second semiconductor die to at least one of said one or more elevated regions on the first side of the second conductive substrate, wherein said one or more contact pads of the first semiconductor die have a different configuration than said one or more contact pads of the second semiconductor die.