Embedded wire bond wires

• US 10,490,528 B2
• Filed: 01/12/2016
• Issued: 11/26/2019
• Est. Priority Date: 10/12/2015
• Status: Active Grant

• Current Assignee: Invensas LLC (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Prabhu, Ashok S., Awujoola, Abiola, Zohni, Wael, Subido, Willmar
• Primary Examiner(s): Parker, Allen L
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US14/993,586
• Publication Number:
  US 20170103968A1
• Time in Patent Office: 1,414 Days
• CPC Class Codes: H01L 2224/42 Wire connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/44 Structure, shape, material or disposition of the wire connectors prior to the connecting process
• CPC Class Codes: H01L 2224/45 of an individual wire connector
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/45164 Palladium (Pd) as principal constituent
• CPC Class Codes: H01L 2224/46 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/47 Structure, shape, material or disposition of the wire connectors after the connecting process
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/49051 Connectors having different shapes
• CPC Class Codes: H01L 2224/49052 Different loop heights
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/06537 Electromagnetic shielding
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/3157 Partial encapsulation or coating mask layer used as insulation layer H01L21/31
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/01 Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/42 Wire connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/44 : Structure, shape, material or disposition of the wire connectors prior to the connecting process
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/47 : Structure, shape, material or disposition of the wire connectors after the connecting process
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/20755 : larger or equal to 50 microns less than 60 microns

Abstract

Apparatuses relating generally to a vertically integrated microelectronic package are disclosed. In an apparatus thereof, a substrate has an upper surface and a lower surface opposite the upper surface. A first microelectronic device is coupled to the upper surface of the substrate. The first microelectronic device is a passive microelectronic device. First wire bond wires are coupled to and extend away from the upper surface of the substrate. Second wire bond wires are coupled to and extend away from an upper surface of the first microelectronic device. The second wire bond wires are shorter than the first wire bond wires. A second microelectronic device is coupled to upper ends of the first wire bond wires and the second wire bond wires. The second microelectronic device is located above the first microelectronic device and at least partially overlaps the first microelectronic device.

Claims

1. A vertically integrated microelectronic package, comprising:

a substrate having an upper surface and a lower surface opposite the upper surface;

a first microelectronic device coupled to the upper surface of the substrate, the first microelectronic device being a passive microelectronic device;

first wire bond wires coupled to and extending away from the upper surface of the substrate;

second wire bond wires coupled to and extending away from an upper surface of the first microelectronic device, the second wire bond wires being shorter than the first wire bond wires;

a second microelectronic device coupled to upper ends, including corresponding tips, of the first wire bond wires and the second wire bond wires, the second microelectronic device located above the first microelectronic device and at least partially overlapping the first microelectronic device;

a molding layer having an uppermost surface and a lowermost surface opposite the uppermost surface, the molding layer disposed for surrounding portions of lengths of a first subset of the first wire bond wires and portions of lengths of second wire bond wires;

wherein the upper ends of the first subset of the first wire bond wires, the upper ends of the second subset of the first wire bond wires and the upper ends of the second wire bond directly interconnect the second microelectronic device above the uppermost surface of the molding layer;

wherein the second subset of the first wire bond wires are located outside of the molding layer;

the first microelectronic device is disposed in the molding layer and completely located between the uppermost surface and the lowermost surface of the molding layer;

the second microelectronic device is coupled above the uppermost surface of the molding layer;

a third microelectronic device coupled to and located above the second microelectronic device and at least partially overlapping the second microelectronic device;

wherein the third microelectronic device is coupled above the uppermost surface of the molding layer; and

wherein both the first microelectronic device and the third microelectronic device are in a face-down orientation for facing the upper surface of the substrate.

2. The vertically integrated microelectronic package according to claim 1, wherein the second microelectronic device is a passive microelectronic device.

3. The vertically integrated microelectronic package according to claim 1, wherein the second microelectronic device is an active microelectronic device.

4. The vertically integrated microelectronic package according to claim 1, wherein both the first microelectronic device and the second microelectronic device are in a face-down orientation for facing the upper surface of the substrate.

5. The vertically integrated microelectronic package according to claim 1, wherein the second microelectronic device and the third microelectronic device are respective passive microelectronic devices.

6. The vertically integrated microelectronic package according to claim 1, wherein the second microelectronic device and the third microelectronic device respectively are another passive microelectronic device and an active microelectronic device.

7. The vertically integrated microelectronic package according to claim 1, wherein

the third microelectronic device is an active microelectronic device.

8. A vertically integrated microelectronic package, comprising:

a substrate having an upper surface and a lower surface opposite the upper surface;

a first microelectronic device coupled to the upper surface of the substrate, the first microelectronic device being a passive microelectronic device;

first wire bond wires coupled to and extending away from the upper surface of the substrate;

second wire bond wires coupled to and extending away from an upper surface of the first microelectronic device;

a first portion of the first wire bond wires being taller than the second wire bond wires;

a second microelectronic device coupled to first upper ends of the first portion the first wire bond wires and coupled to upper ends, including corresponding tips, of the second wire bond wires, the second microelectronic device located above the first microelectronic device and at least partially overlapping the first microelectronic device;

a second portion of the first wire bond wires having second upper ends thereof coupled to the upper surface of the first microelectronic device;

a molding layer having an uppermost surface and a lowermost surface opposite the uppermost surface disposed for surrounding lengths of both the first wire bond wires and the second wire bond wires with the first upper ends of the first portion of the first wire bond wires and the upper ends of the second wire bond wires directly interconnected to the second microelectronic device above the uppermost surface;

the first microelectronic device disposed in the molding layer and completely located between the uppermost surface and the lowermost surface of the molding layer;

the second microelectronic device coupled above the uppermost surface of the molding layer;

a third microelectronic device coupled to and located above the second microelectronic device and at least partially overlapping the second microelectronic device;

wherein the third microelectronic device is coupled above the uppermost surface of the molding layer; and

wherein both the first microelectronic device and the third microelectronic device are in a face-down orientation for facing the upper surface of the substrate.

9. The vertically integrated microelectronic package according to claim 8, wherein the second microelectronic device and the third microelectronic device are respective passive microelectronic devices.

10. The vertically integrated microelectronic package according to claim 8, wherein the second microelectronic device and the third microelectronic device respectively are another passive microelectronic device and an active microelectronic device.