Three-dimensional vertical one-time-programmable memory comprising multiple antifuse sub-layers

• US 10,490,562 B2
• Filed: 03/13/2018
• Issued: 11/26/2019
• Est. Priority Date: 04/16/2016
• Status: Expired due to Fees

• Current Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Trinh, Michael M
• Application Number:
  US15/919,381
• Publication Number:
  US 20180204844A1
• Time in Patent Office: 623 Days
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/73 Array where access device function, e.g. diode function, being merged with memorizing function of memory element
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 20/25 One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type

Abstract

The present invention discloses a three-dimensional vertical one-time-programmable memory (3D-OTP_V). It comprises horizontal address lines and memory holes there-through, an antifuse layer and vertical address lines in said memory holes. The antifuse layer comprises at least first and second sub-layers with different antifuse materials. The 3D-OTP_V comprises no separate diode layer.

Claims

1. A three-dimensional vertical one-time-programmable memory (3D-OTP_V), comprising:

a semiconductor substrate comprising a substrate circuit;

a plurality of vertically stacked horizontal address lines above said semiconductor circuit, wherein said horizontal address lines comprise at least a first conductive material;

a plurality of memory holes through said horizontal address lines;

an antifuse layer on the sidewalls of said memory holes, said antifuse layer comprising at least first and second sub-layers, wherein said first and second sub-layers comprise different antifuse materials;

a plurality of vertical address lines in said memory holes and in contact with said anitfuse layer, wherein said vertical address lines comprise at least a second conductive material;

a plurality of OTP cells at the intersections of said horizontal and vertical address lines, wherein each of said OTP cells comprises at least a first portion of a first selected one of said horizontal address lines, at least a second portion of a second selected one of said vertical address lines, and at least a third portion of said antifuse layer;

wherein said horizontal and vertical address lines are separated by said antifuse layer only.

2. The 3D-OTP_V according to claim 1, wherein said first sub-layer comprises at least a metal oxide or silicon oxide, and second sub-layer comprise at least a metal nitride or silicon nitride.

3. The 3D-OTP_V according to claim 1, further comprising:

a first interface between said first sub-layer and selected one of said horizontal address lines;

a second interface between said second sub-layer and selected one of said vertical address lines;

wherein said first and second interfaces are different.

4. The 3D-OTP_V according to claim 1, wherein said first and second conductive materials are different conductive materials.

5. The 3D-OTP_V according to claim 1, wherein said horizontal address line, said antifuse layer and said vertical address line form a built-in diode.

6. The 3D-OTP_V according to claim 5, wherein the resistance of said diode is substantially lower than when the applied voltage has a magnitude smaller than or a polarity opposite to that of the read voltage.

7. The 3D-OTP_V according to claim 6, wherein all OTP cells coupled to a selected horizontal address line are read out in a single read cycle.

8. The 3D-OTP_V according to claim 7, wherein the I-V characteristics of said built-in diode satisfies |(V_R)>

>

n*I(−

V_T), where V_R is the read voltage on said selected horizontal address line;

V_T is the toggle voltage of a selected vertical address line;

n is the number of OTP cells on said selected horizontal address line.

9. The 3D-OTP_V according to claim 1, wherein said OTP cells form an OTP string.

10. The 3D-OTP_V according to claim 9, further comprising a vertical transistor coupled to said OTP string.

11. The 3D-OTP_V according to claim 10, wherein said vertical transistor is formed in a first portion of said memory hole, and said OTP string is formed in a second portion of said memory hole.