Semiconductor devices comprising nitrogen-doped gate dielectric, and methods of forming semiconductor devices

• US 10,490,645 B2
• Filed: 08/14/2018
• Issued: 11/26/2019
• Est. Priority Date: 11/30/2016
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Moriwaki, Yoshikazu
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US16/103,052
• Publication Number:
  US 20190027412A1
• Time in Patent Office: 469 Days
• CPC Class Codes: H01L 21/28158 Making the insulator
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/31155 by ion implantation
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

Some embodiments include semiconductor devices having first transistors of a first channel type and having second transistors of a second channel type. The first transistors include a first gate electrode, a first nitrogen-doped gate dielectric layer and a first high-k material. The second transistors include a second gate electrode, a second nitrogen-doped gate dielectric layer and a second high-k material. The second nitrogen-doped gate dielectric layer is doped with nitrogen to a different peak concentration than the first nitrogen-doped gate dielectric layer. Some embodiments include methods of forming PMOS and NMOS transistors having nitrogen-doped gate dielectric material.

Claims

1. A semiconductor device comprising:

a first transistor of a first channel type, wherein the first transistor comprises;

a first gate electrode;

a first nitrogen-doped gate dielectric layer;

the first nitrogen-doped gate dielectric layer being doped with nitrogen to a first peak concentration; and

a first high-k material between the first nitrogen-doped gate dielectric layer and the first gate electrode, the first high-k material not comprising nitrogen therein; and

a second transistor of a second channel type, wherein the second transistor comprises;

a second gate electrode;

a second nitrogen-doped gate dielectric layer;

the second nitrogen-doped gate dielectric layer being doped with nitrogen and to a second peak concentration which is different from the first peak concentration; and

a second high-k material between the second nitrogen-doped gate dielectric layer and the second gate electrode, the second high-k material not comprising nitrogen therein.

2. The semiconductor device according to claim 1, wherein the first channel type is p-type and the second channel type is n-type, and wherein the first peak concentration is less than the second peak concentration.

3. The semiconductor device according to claim 1, wherein the nitrogen is doped in the second nitrogen-doped gate dielectric layer to the second peak concentration and to a third peak concentration, and wherein the second peak concentration is greater than the third peak concentration.

4. The semiconductor device according to claim 3, wherein the first peak concentration is greater than the third peak concentration and smaller than the second peak concentration.

5. The semiconductor device according to claim 1, wherein the first nitrogen-doped gate dielectric layer and the second nitrogen-doped gate dielectric layer both comprise silicon oxide.

6. The semiconductor device according to claim 1, wherein the first high-k material comprises hafnium oxide and aluminum oxide, and the second high-k material comprises hafnium oxide.

7. The semiconductor device according to claim 1, wherein a thickness of each of the first nitrogen-doped gate dielectric layer and the second nitrogen-doped gate dielectric layer is within a range of from about 1.8 nm to about 5.8 nm.

8. The semiconductor device according to claim 1, wherein the first peak concentration of nitrogen of the first nitrogen-doped gate dielectric layer is located within an area from a bottom surface of the first nitrogen-doped gate dielectric layer to a height of 1 nm, and wherein the second peak concentration of nitrogen of the second nitrogen-doped gate dielectric layer is located within an area from a bottom surface of the second nitrogen-doped gate dielectric layer to a height of 1 nm.

9. A semiconductor device comprising:

a PMOS transistor having a first nitrogen-doped gate dielectric layer doped with nitrogen to a first concentration, the PMOS transistor having a pair of p-type source/drain regions;

an NMOS transistor having a second nitrogen-doped gate dielectric layer doped with nitrogen to a second concentration;

wherein the second concentration is at least about 30% greater than the first concentration, the NMOS transistor having a pair of n-type source/drain regions; and

wherein the PMOS transistor and the NMOS transistor are directly adjacent to one another and together comprised by a CMOS;

one of the n-type source/drain regions of the NMOS transistor being spaced from one of the p-type source/drain regions of the PMOS transistor by intervening insulative material of an isolation region, said intervening insulative material directly contacting both said one of the n-type source/drain regions and said one of the p-type source/drain regions.

10. The semiconductor device according to claim 9, wherein the nitrogen is doped in the first nitrogen-doped gate dielectric layer to a first peak concentration, wherein the nitrogen is doped in the second nitrogen-doped gate dielectric layer to a second peak concentration and a third peak concentration, and wherein the second peak concentration is greater than the first and third peak concentrations.

11. The semiconductor device according to claim 9, wherein the first and second nitrogen-doped gate dielectric layers comprise a common composition as one another.

12. The semiconductor device according to claim 9, wherein the first and second nitrogen-doped gate dielectric layers both comprise silicon oxide.

13. A semiconductor device comprising:

a first transistor of a first conductivity type, wherein the first transistor comprises;

a first gate electrode;

a first gate dielectric layer, wherein the first gate dielectric layer is doped with nitrogen; and

a second gate dielectric layer, wherein the second gate dielectric layer intervenes between the first gate dielectric layer and the first gate electrode and includes a first high-k material; and

a second transistor of a second conductivity type, wherein the second transistor comprises;

a second gate electrode;

a third gate dielectric layer, wherein the third gate dielectric layer is doped with nitrogen and is different in peak concentration of nitrogen from the first gate dielectric layer; and

a fourth gate dielectric layer, wherein the fourth gate dielectric layer intervenes between the third gate dielectric layer and the second gate electrode and includes a second high-k material.

14. The semiconductor device according to claim 13, wherein the first conductivity type is an N type and the second conductivity type is a P type, and wherein the peak concentration of nitrogen of the first gate dielectric layer is greater than the peak concentration of nitrogen of the third gate dielectric layer.

15. The semiconductor device according to claim 13, wherein the nitrogen is doped in the first gate dielectric layer to represent first peak concentration and second peak concentration, and wherein the first peak concentration is greater than the second peak concentration.

16. The semiconductor device according to claim 13, wherein each of the first and third gate dielectric layers comprises silicon oxide.

17. The semiconductor device according to claim 13, wherein the first high-k material comprises hafnium oxide, and the second high-k material comprises hafnium oxide and aluminum oxide.

18. The semiconductor device according to claim 15, wherein the peak concentration of nitrogen of the third gate dielectric layer is greater than the second peak concentration and smaller than the first peak concentration.

19. The semiconductor device according to claim 13 wherein a thickness of each of the first gate dielectric layer and the third gate dielectric layers is within a range from substantially 1.8 nm to substantially 5.8 nm.

20. The semiconductor device according to claim 13 wherein the peak concentration of nitrogen of the first gate dielectric layer is located within an area from a bottom surface of the first gate dielectric layer to height of 1.0 nm, and wherein the peak concentration of nitrogen of the third gate dielectric layer is located within an area from a bottom surface of the third gate dielectric layer to height of 1.0 nm.