Optoelectronic semiconductor chip and method of producing the same

• US 10,490,698 B2
• Filed: 09/22/2015
• Issued: 11/26/2019
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: OSRAM OLED GMBH (Ams-Osram AG)
• Original Assignee: Osram Opto Semiconductors GmbH (Ams-Osram AG)
• Inventors: Klemp, Christoph
• Primary Examiner(s): Chin, Edward
• Application Number:
  US15/514,652
• Publication Number:
  US 20170222088A1
• Time in Patent Office: 1,526 Days
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/14 with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector

Abstract

An optoelectronic semiconductor chip includes a semiconductor layer sequence and a carrier substrate, wherein the semiconductor layer sequence includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged between the first semiconductor region and the second semiconductor region, wherein the first semiconductor region faces the carrier substrate, the semiconductor layer sequence includes first recesses formed in the first semiconductor region and that do not separate the active layer, the semiconductor layer sequence includes second recesses that at least partially separate the first semiconductor region and the active layer, and the second recesses adjoin a first recess or are arranged between two first recesses.

Claims

1. An optoelectronic semiconductor chip comprising a semiconductor layer sequence and a carrier substrate, wherein

the semiconductor layer sequence comprises a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged between the first semiconductor region and the second semiconductor region, wherein the first semiconductor region faces the carrier substrate,

the semiconductor layer sequence comprises first recesses formed in the first semiconductor region and that do not separate the active layer,

the semiconductor layer sequence comprises second recesses that at least partially separate the first semiconductor region and the active layer,

the second recesses adjoin a first recess or are arranged between two first recesses, and

the first recesses and the second recesses comprise oblique side surfaces that enclose an angle of 30°

to 60°

with the first main surface of the semiconductor layer sequence facing the carrier substrate.

2. The optoelectronic semiconductor chip according to claim 1, wherein regions of a first main surface of the semiconductor layer sequence arranged between a second recess and a neighboring first recess are not electrically contacted.

3. The optoelectronic semiconductor chip according to claim 1, wherein the first recesses and/or the second recesses have a depth of 0.1 μ

m to 10 μ

m.

4. The optoelectronic semiconductor chip according to claim 1, wherein the first recesses and/or the second recesses have a cross-sectional area that decreases from the carrier substrate.

5. The optoelectronic semiconductor chip according to claim 1, wherein the first recesses and/or the second recesses have a trapezoidal cross-sectional area.

6. The optoelectronic semiconductor chip according to claim 1, wherein the first recesses and/or the second recesses are prism-shaped.

7. The optoelectronic semiconductor chip according to claim 1, wherein the first recesses have a greater width than the second recesses, and the second recesses adjoin a first recess when viewed from the carrier substrate in each case in a vertical direction.

8. The optoelectronic semiconductor chip according to claim 1, wherein the first recesses have a width of 20 μ

m to 50 μ

m and the second recesses have a width of 2 μ

m to 20 μ

m.

9. The optoelectronic semiconductor chip according to claim 1, wherein the width of the first recesses is greater than a width of the second recesses by at least 10 μ

m.

10. The optoelectronic semiconductor chip according to claim 1, wherein the second recesses do not directly adjoin the first recesses and are each arranged between two of the first recesses.

11. The optoelectronic semiconductor chip according to claim 10, wherein the first recesses have a lateral distance of at least 20 μ

m and 50 μ

m at the most, and the second recesses have a width of 2 μ

m to 20 μ

m.