Switch linearizer

• US 10,491,209 B2
• Filed: 07/17/2013
• Issued: 11/26/2019
• Est. Priority Date: 07/17/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Dicicco, Marc Gerald, Zhang, Xiangdong, Wang, Xinwei
• Primary Examiner(s): Kessie, Daniel
• Assistant Examiner(s): Chowdhuri, Swarna N
• Application Number:
  US13/944,709
• Publication Number:
  US 20150022024A1
• Time in Patent Office: 2,323 Days
• Field of Search: 307109
• CPC Class Codes: H03K 17/16 Modifications for eliminating interference voltages or currents
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

Exemplary embodiments are related to switch linearizer. A device may include at least one switch. The device may further include a linearizer coupled to the at least one switch and configured to cancel at least a portion of distortion generated by the at least one switch in an off-state.

Claims

1. A device comprising:

an antenna tuning circuit comprising a digital variable capacitor (DVC), the DVC comprising;

a first plurality of switches coupled in series between a first terminal and a second terminal;

a first linearizer coupled to the first terminal and to the second terminal and coupled in parallel with the plurality of switches, the linearizer comprising at least one first varactor having an adjustable capacitance responsive to a tuning voltage;

a second plurality of switches coupled in series between the first terminal and the second terminal; and

a second linearizer coupled between the first terminal and the second terminal, the second linearizer coupled in parallel with the second plurality of switches and comprising at least one second varactor, wherein the first linearizer is configured to compensate for 3^rd order distortion generated by the plurality of switches, and wherein the second linearizer is configured to compensate for 3^rd order distortion generated by the second plurality of switches.

2. The device of claim 1, the first plurality of switches comprising a plurality of stacked transistors.

3. The device of claim 1, the first linearizer further comprising a plurality of metal-insulator-metal (MIM) capacitors coupled in series with the at least one varactor.

4. The device of claim 1, the first linearizer configured to generate 3^rd order distortion having an amplitude substantially equal to an amplitude of 3^rd order distortion generated by the first plurality of switches and a phase substantially opposite of a phase of the 3^rd order distortion generated by the first plurality of switches.

5. The device of claim 1, the first plurality of switches configured to generate a positive 3^rd order distortion term and the first linearizer configured to generate a negative 3^rd order distortion term.

6. The device of claim 1, the first linearizer configured to generate 3^rd order distortion to destructively interfere with 3^rd order distortion generated by the first plurality of switches.

13. The device of claim 1, further comprising a first capacitor coupled between the first terminal and the at least one first varactor.

14. The device of claim 13, further comprising a second capacitor coupled between the second terminal and the at least one first varactor.

15. The device of claim 13, wherein the first capacitor comprises a metal-insulator-metal (MIM) capacitor.

16. The device of claim 1, wherein the at least one first varactor comprises a first variable capacitor in series with a second variable capacitor.

17. The device of claim 1, further comprising:

a first metal-insulator-metal (MIM) capacitor coupled in series with the at least one first varactor, the first MIM capacitor coupled between the first terminal and the at least one first varactor; and

a second MIM capacitor coupled in series with the first MIM capacitor and the at least one first varactor, the second MIM capacitor coupled between the second terminal and the at least one first varactor.

7. A method comprising:

configuring a first plurality of switches in an off-state, the first plurality of switches coupled in series between a first terminal and a second terminal;

cancelling at least a portion of 3^rd order distortion generated by the first plurality of switches in the off-state with distortion generated by at least one first varactor that is included in a first linearizer coupled between the first terminal and the second terminal and in parallel with the first plurality of switches, the at least one first varactor having an adjustable capacitance responsive to a tuning voltage;

configuring a second plurality of switches coupled in series between the first terminal and the second terminal; and

cancelling at least a portion of 3^rd order distortion generated by the second plurality of switches with distortion generated by at least one second varactor that is included in a second linearizer coupled between the first terminal and the second terminal and in parallel with the second plurality of switches.

8. The method of claim 7, wherein cancelling the at least a portion of the 3^rd order distortion generated by the first plurality of switches comprises generating 3^rd order distortion of the first varactor to constructively interfere with 3^rd order distortion generated by the first plurality of switches.

9. The method of claim 7, further comprising adjusting the tuning voltage conveyed to the first varactor to adjust a magnitude of a 3^rd order term of a capacitance of the first varactor.

10. A device comprising:

means for tuning an antenna comprising means for providing a digital variable capacitance, the means for providing the digital variable capacitance comprising;

means for configuring a first plurality of switches in an off-state, the first plurality of switches coupled in series between a first terminal and a second terminal;

means for cancelling at least a portion of 3^rd order distortion of the first plurality of switches in the off-state, the means for cancelling at least a portion of 3^rd order distortion of the first plurality of switches coupled between the first terminal and the second terminal and in parallel with the first plurality of switches, and the means for cancelling at least a portion of 3^rd order distortion of the first plurality of switches having a first adjustable capacitance based on a tuning voltage;

means for configuring a second plurality of switches coupled in series between the first terminal and the second terminal; and

means for cancelling at least a portion of 3^rd order distortion generated by the second plurality of switches, the means for cancelling at least a portion of 3^rd order distortion of the second plurality of switches coupled between the first terminal and the second terminal and in parallel with the second plurality of switches, and the means for cancelling at least a portion of 3^rd order distortion of the second plurality of switches having a second adjustable capacitance.

11. The device of claim 10, wherein the means for cancelling at least a portion of 3^rd order distortion of the first plurality of switches comprises at least one varactor.

12. The device of claim 10, the means for configuring the first plurality of switches comprising means for conveying a bias voltage to the first plurality of switches to configure the first plurality of switches in the off-state.