Memory decision feedback equalizer testing

• US 10,491,430 B2
• Filed: 09/25/2017
• Issued: 11/26/2019
• Est. Priority Date: 09/25/2017
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sreeramaneni, Raghukiran, Taylor, Jennifer E., Liu, Liang
• Primary Examiner(s): Tadese, Berhanu
• Application Number:
  US15/714,818
• Publication Number:
  US 20190097846A1
• Time in Patent Office: 792 Days
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03146 with a recursive structure H04L25/03127 takes precedence

Abstract

A device includes one or more memory banks configured to store data. The device also includes a data receiver configured to receive distorted input data as part of a data stream, apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data, and generate the data by applying the correction factor to the distorted data. The device further includes a test circuit internal to the device, wherein the test circuit is configured to generate the data stream.

Claims

1. A memory device, comprising:

one or more memory banks configured to store data;

a data receiver configured to;

receive distorted input data as part of a data stream;

apply a correction factor to the distorted input data to offset inter-symbol interference from the data stream on the distorted input data; and

generate the data by applying the correction factor to the distorted data; and

a test circuit internal to the memory device, wherein the test circuit is configured to generate the data stream.

2. The memory device of claim 1, comprising a transmitter coupled to the one or more memory banks, wherein the transmitter is configured to receive the second data from the memory banks when the memory device operates in a first mode of operation.

3. The memory device of claim 2, wherein the test circuit is coupled to the transmitter, wherein the transmitter is configured to receive the data stream from the test circuit when the memory device operates in a second mode of operation.

4. The memory device of claim 3, wherein the transmitter comprises a plurality of transmitter legs coupled to an output connector of the memory device.

5. The memory device of claim 4, wherein the plurality of transmitter legs are additionally coupled to the receiver.

6. The memory device of claim 5, wherein the test circuit is configured to generate control signals to control selective activation of each transmitter leg of the plurality of transmitter legs.

7. The memory device of claim 6, wherein the selectively activated transmitter legs of the plurality of transmitter legs transmit the distorted input data based on the data stream received from the test circuit.

8. The memory device of claim 5, wherein the test circuit is configured to generate control signals to control the selective activation and respective strength of each transmitter leg of the plurality of transmitter legs.

9. The memory device of claim 8, wherein the selectively activated transmitter legs of the plurality of transmitter legs transmit the distorted input data based on the data stream received from the test circuit.

10. A semiconductor device, comprising:

a test circuit internal to the device, wherein the test circuit is configured to;

generate a data stream comprising a data value; and

generate a control signal;

a data transmitter configured to alter a characteristic of the data value of the data stream based upon the control signal; and

a data receiver configured to receive the data value having an altered characteristic and apply an inverse value of the altered characteristic to the data value to regenerate the data value.

11. The semiconductor device of claim 10, wherein the data receiver is configured to transmit the regenerated data value to the test circuit.

12. The semiconductor device of claim 11, wherein the test circuit is configured to compare the regenerated data value with the data value.

13. The semiconductor device of claim 12, wherein the test circuit is configured to generate an indication that the data receiver is malfunctioning based upon the comparison of the regenerated data value with the data value.

14. The semiconductor device of claim 10, wherein the data receiver is configured to transmit the regenerated data value to one or more memory banks configured to store data.

15. The semiconductor device of claim 14, wherein the one or more memory banks are configured to transmit the regenerated data value to the test circuit.

16. The semiconductor device of claim 14, wherein the one or more memory banks are configured to transmit the regenerated data value to an external test circuit coupled to the semiconductor device.

17. The semiconductor device of claim 10, comprising:

a second data transmitter configured to alter a characteristic of the data value of the data stream based upon the control signal;

a second data receiver configured to receive the data value having an altered characteristic and apply an inverse value of the altered characteristic to the data value to regenerate the data value.

18. A method, comprising:

placing a semiconductor device into a testing mode of operation;

internally generating a data stream comprising a data value in the semiconductor device;

internally generating a control signal configured to activate transmission legs of a transmitter at a particular strength in the semiconductor device;

transmitting the data value from at least one activated transmission leg as an input data signal; and

applying decision feedback equalization to the input data signal to correct for inter-symbol interference distortion of the input data signal to generate an equalized data value.

19. The method of claim 18, comprising transmitting the equalized data value to memory of the semiconductor for storage.

20. The method of claim 19, comprising reading the equalized data value from memory and transmitting the equalized data value to an internal test circuit of the semiconductor device.

21. The method of claim 20, comprising comparing the equalized data value with the data value in the internal test circuit.

22. The method of claim 21, comprising generating an indication indicative of the correct functioning of the decision feedback equalization of the semiconductor device based upon the comparison of the generated data value with the data value.

23. The method of claim 18, comprising transmitting the equalized data value to an internal test circuit of the semiconductor device.

24. The method of claim 23, comprising comparing the equalized data value with the data value and generating an indication indicative of the correct functioning of the decision feedback equalization of the semiconductor device based upon the comparison of the generated data value with the data value.

25. A memory testing device, comprising:

a processor configured to;

receive an indication of tap values to be applied by decision feedback circuitry of a memory device; and

generate a modified data stream to mimic inter-symbol interference of a data stream correctable by the tap values; and

an output configured to transmit the modified data stream as an input data stream to the memory device.

26. The memory testing device of claim 25, comprising an input configured to receive the indication of tap values from the memory device.

27. The memory testing device of claim 25, comprising an input configured to receive the indication of tap values from a user.

28. The memory testing device of claim 25, comprising an input configured to receive an output data stream from the memory device.

29. The memory testing device of claim 28, wherein the processor is configured to initiate comparison of the output data stream with the data stream to verify correction functioning of the decision feedback circuitry.

30. The memory testing device of claim 29, wherein the processor is configured to generate an indication of the comparison for display or for storage in the memory device or the memory testing device.

31. A tangible non-transitory computer-readable medium having computer executable code stored thereon, the code comprising instructions to cause a processor to:

generate a data stream;

transmit the data stream to a semiconductor device;

receive a first output data stream from the semiconductor device, wherein the first output data stream comprises a decision feedback equalized data stream of the input data stream;

generate a modified data stream to mimic inter-symbol interference of the data stream correctable by decision feedback equalization circuitry of the memory device; and

receive a second output data stream from the semiconductor device, wherein the second output data stream comprises a decision feedback equalized data stream of the modified data stream.

32. The tangible non-transitory computer-readable medium of claim 31, wherein the code comprises instructions to generate a first data eye diagram based on the first output data stream.

33. The tangible non-transitory computer-readable medium of claim 32, wherein the code comprises instructions to generate a second data eye diagram based on the second output data stream.

34. The tangible non-transitory computer-readable medium of claim 33, wherein the code comprises instructions to generate an output of the first data eye diagram and the second data eye diagram to indicate whether the first data eye diagram matches the second data eye diagram.