Method and system using ternary sequences for simultaneous transmission to coherent and non-coherent receivers

• US 10,491,434 B2
• Filed: 12/28/2018
• Issued: 11/26/2019
• Est. Priority Date: 10/29/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jos, Sujit, PS, Chandrashekhar Thejaswi, Bynam, Kiran, Hong, Young Jun, Park, Chang Soon, Choudhary, Manoj
• Primary Examiner(s): Bayard, Emmanuel
• Application Number:
  US16/235,222
• Publication Number:
  US 20190140868A1
• Time in Patent Office: 333 Days
• Field of Search: 375287, 375295, 375343
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04L 25/03312 Arrangements specific to the provision of output signals
• CPC Class Codes: H04L 25/03834 using pulse shaping
• CPC Class Codes: H04L 25/4923 using ternary codes H04L25/4927 takes precedence
• CPC Class Codes: H04L 27/04 Modulator circuits; Transmitter circuits
• CPC Class Codes: H04W 28/18 Negotiating wireless communication parameters
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

The present invention describes a method and system for simultaneous transmission of data to coherent and non-coherent receivers. The method at the transmitter includes retrieving a base ternary sequence having a pre-defined length, obtaining one or more ternary sequences corresponding to data to be transmitted and transmitting the obtained one or more ternary sequences by the transmitter. The method steps at the receiver includes receiving one or more ternary sequences corresponding to the data transmitted, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the base ternary sequence by the receiver if the receiver is a coherent receiver, demodulating each of the received ternary sequences by correlating with all cyclic shifts of the absolute of the base ternary sequence by the receiver if the receiver is a non-coherent receiver and detecting the transmitted data based on the cyclic shifts corresponding to maximum correlation values.

Claims

1. A method of data-symbol-to-chip mapping, the method comprising:

generating data symbols based on input bits; and

mapping the data symbols to a set of ternary sequences,

wherein the mapping is determined by a k/L-TASK (Ternary Amplitude Shift Keying) modulation format,

wherein the k denotes a size of each of the data symbols, and the L denotes a length of each of the ternary sequences, and

wherein the set of ternary sequences comprises a ternary sequence c₀ and a ternary sequence c_m, the c_m being cyclic shifted from the c₀ by m locations, the m being an integer.

2. The method of claim 1, wherein the m is an integer no greater than the L.

3. The method of claim 1, wherein the c_m is a cyclic shifted from the c₀ by the m locations to a right.

4. The method of claim 3,

wherein the c₀ is {0 0 0 1 −

1 0 1 1} in case of a 3/8-TASK modulation format being applied, and

wherein the c₀ is {−

1 0 0 1 0 1 −

1 0 −

1 −

1 1 −

1 0 1 0 1 0 0 0 1 0 0 1 1 −

1 0 0 0 0 0 1 1} in case of a 5/32-TASK modulation format being applied.

5. The method of claim 1,

wherein in case of a 3/8-TASK modulation format being applied, a number of the data symbols are 8, and

wherein the 8 data symbols are mapped to 8-length ternary sequences.

6. The method of claim 1, wherein in case of a 3/8-TASK modulation format being applied, the c₀ corresponding to a data symbol “

0”

is obtained, the c₀ being {0 0 0 1 −

1 0 1 1}.

7. The method of claim 1,

wherein in case of a 5/32-TASK modulation format being applied, a number of the data symbols are 32, and

wherein the 32 data symbols are mapped to 32-length ternary sequences.

8. The method of claim 1, wherein the length of each of the ternary sequences is 2^k.

9. The method of claim 1, wherein the set of ternary sequences comprises a ternary sequence c₀ and a ternary sequence c_m, the c_m being cyclic shifted from the c₀ by m locations, the m being an integer.

10. An apparatus for performing data-symbol-to-chip mapping, the apparatus comprising:

a processor configured to generate data symbols based on input bits, and map the data symbols to a set of ternary sequences,

wherein the mapping is determined by a k/L-TASK (Ternary Amplitude Shift Keying) modulation format, and

wherein the k denotes a size of each of the data symbols, and the L denotes a length of each of the ternary sequences.

11. The apparatus of claim 10, wherein the m is an integer no greater than the L.

12. The apparatus of claim 10, wherein the c_m is cyclic shifted from the c₀ by the m locations.

13. The apparatus of claim 12,

wherein the c₀ is {0 0 0 1 −

1 0 1 1} in case of a 3/8-TASK modulation format being used, and

wherein the c₀ is {−

1 0 0 1 0 1 −

1 0 −

1 −

1 1 −

1 0 1 0 1 0 0 0 1 0 0 1 1 −

1 0 0 0 0 0 1 1} in case of a 5/32-TASK modulation format being used.

14. The apparatus of claim 10,

wherein in case of a 3/8-TASK modulation format being used, a number of the data symbols are 8, and

wherein the 8 data symbols are mapped to 8-length ternary sequences.

15. The apparatus of claim 10, wherein in case of a 3/8-TASK modulation format being used, the c₀ corresponding to a data symbol “

0”

is obtained, the c₀ being {0 0 0 1 −

1 0 1 1}.

16. The apparatus of claim 10,

wherein in case of a 5/32-TASK modulation format being applied, a number of the data symbols are 32, and

wherein the 32 data symbols are mapped to 32-length ternary sequences.

17. The apparatus of claim 10, wherein the length of each of the ternary sequences is 2^k.

18. The apparatus of claim 10, wherein the set of ternary sequences comprises a ternary sequence c₀ and a ternary sequence c_m, the c_m being cyclic shifted from the c₀ by m locations, the m being an integer.