Apparatus and method for hardware initiation of emulated instructions

• US 10,496,461 B2
• Filed: 06/15/2011
• Issued: 12/03/2019
• Est. Priority Date: 06/15/2011
• Status: Active Grant

• Current Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Original Assignee: ARM Finance Overseas Limited (SoftBank Group Corp.)
• Inventors: Lau, David Yiu-Man
• Primary Examiner(s): Gebresilassie, Kibrom K
• Application Number:
  US13/161,354
• Publication Number:
  US 20120323552A1
• Time in Patent Office: 3,093 Days
• Field of Search: None
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0772 Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
• CPC Class Codes: G06F 2009/45591 Monitoring or debugging support
• CPC Class Codes: G06F 9/3865 using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/455 Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
• CPC Class Codes: G06F 9/45504 Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators

Abstract

A method of emulating an instruction includes identifying a fault instruction. The fault instruction is saved in a register. The fault instruction is associated with a software emulated operation. The software emulated operation is initiated with an access to the fault instruction in the register.

Claims

1. A method of emulating an instruction, comprising:

fetching an instruction with a processor;

decoding the fetched instruction with the processor;

determining, prior to execution of the decoded instruction, whether the decoded instruction is executable by a hardware resource within or coupled to the processor;

when it is determined that the decoded instruction is executable by the hardware resource, identifying, with the processor, prior to execution of the decoded instruction, a fault instruction by determining whether the decoded instruction is allowed in an execution mode, and executing the decoded instruction when the decoded instruction is allowed in the execution mode, and, upon identifying the fault instruction when the decoded instruction is not allowed in the execution mode;

saving the fault instruction in a fault register on the processor,

associating the fault instruction in the fault register on the processor with a software emulated operation,

signaling an exception and invoking a software emulator in memory connected to the processor via a bus and executable on the processor in response to the exception,

reading, using the software emulator, the fault instruction in the fault register on the processor,

decoding, using the software emulator, the read fault instruction,

determining, using the software emulator, whether emulation of the decoded fault instruction stored in the fault register is possible,

executing, using the software emulator, the software emulated operation when it is determined that emulation of the fault instruction stored in the fault register is possible.

2. The method of claim 1 further comprising executing the software emulated operation to support a floating point unit operation.

3. A machine, comprising:

a processor including a fault register to store a fault instruction and a configuration register to specify the presence of the fault register; and

a memory connected to the processor via a bus, the memory including instructions executable by the processor to;

fetch an instruction with the processor,

decode the fetched instruction with the processor,

determine, prior to execution of the decoded instruction, whether the decoded instruction is executable by a hardware resource within or coupled to the processor,

when it determined that the instruction is executable by the hardware resource, identify, with the processor prior to execution of the decoded instruction, a fault instruction by determining whether the decoded instruction is allowed in an execution mode, and execute the decoded instruction when the decoded instruction is allowed in the execution mode, and, upon identifying the fault instruction when the decoded instruction is not allowed in the execution mode;

save the fault instruction in the fault register,

associate the fault instruction in the fault register with a software emulated operation,

signal an exception and invoke a software emulator in the memory and executable on the processor in response to the exception,

read, with the software emulator, the fault instruction in the fault register,

decode, with the software emulator, the read fault instruction,

determine, with the software emulator, whether emulation of the fault instruction stored in the fault register is possible, and

execute with the software emulator the software emulated operation when it is determined that emulation of the fault instruction in the fault register is possible.

4. The machine of claim 3 wherein the emulated operation is a floating point unit operation.

5. A processor, comprising:

a fault register to store a fault instruction;

a configuration register to specify the presence of the fault register;

logic executable by the processor to;

fetch an instruction with the processor,

decode the fetched instruction with the processor,

determine, prior to execution of the decoded instruction, whether the decoded instruction is executable by a hardware resource within or coupled to the processor,

when it determined that the instruction is executable by the hardware resource, identify a fault instruction prior to execution of the decoded instruction by determining whether the decoded instruction is allowed in an execution mode, and execute the decoded instruction when the decoded instruction is allowed in the execution mode, and signaling an exception if the decoded instruction is not allowed in the execution mode, and

save the identified fault instruction in the fault register of the processor; and

an exception handler to invoke a software emulated operation utilizing the fault instruction from the fault register, and determine using a software emulator executable on the processor whether emulation of the fault instruction is possible.

6. A non-transitory computer readable storage medium including executable instructions to define a processor, the processor including a fault register to store a fault instruction, a configuration register to specify the presence of the fault register, the non-transitory computer readable storage medium comprising:

logic executable by the processor to;

fetch an instruction with the processor,

decode the fetched instruction with the processor,

determine, prior to execution of the decoded instruction, whether the decoded instruction is executable by a hardware resource in or coupled to the processor,

when it determined that the instruction is executable by the hardware resource, identify a fault instruction by determining whether the decoded instruction is allowed in an execution mode, and executing the decoded instruction when the decoded instruction is allowed in the execution mode, and signaling an exception if the decoded instruction is not allowed in the execution mode, and

save the identified fault instruction in the fault register; and

an exception handler to invoke a software emulated operation in memory connected to the processor via the bus and utilizing an access by a software emulator executable on the processor to the fault instruction from the fault register, and to determine, by the software emulator, whether emulation of the fault instruction is possible.