Implementing DRAM row hammer avoidance

• US 10,497,409 B2
• Filed: 12/17/2014
• Issued: 12/03/2019
• Est. Priority Date: 12/17/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kilmer, Charles A., Lingambudi, Anil B., Maule, Warren E., Vidyapoornachary, Diyanesh B. C.
• Primary Examiner(s): Dudek, Jr., Edward J
• Assistant Examiner(s): Verderamo, III, Ralph A
• Application Number:
  US14/573,142
• Publication Number:
  US 20160180899A1
• Time in Patent Office: 1,812 Days
• Field of Search: None
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 11/408 Address circuits
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A method and apparatus for implementing row hammer avoidance in a dynamic random access memory (DRAM) in a computer system. Hammer detection logic identifies a hit count of repeated activations at a specific row in the DRAM. Monitor and control logic receiving an output of the hammer detection logic compares the identified hit count with a programmable threshold value. Responsive to a specific count as determined by the programmable threshold value, the monitor and control logic captures the address where a selected row hammer avoidance action is provided.

Claims

1. A computer system for implementing row hammer avoidance in a dynamic random access memory (DRAM) comprising:

a processor;

a memory controller coupled between said processor and the dynamic random access memory (DRAM),

said memory controller comprising;

hammer detection logic identifying a hit count of repeated activations at a specific row in the DRAM;

monitor and control logic including a threshold register storing a programmable threshold value, receiving an output of the hammer detection logic for comparing the identified hit count value with said programmable threshold value, said monitor and control logic capturing an address responsive to the compared values and said monitor and control logic providing a selected row hammer avoidance action for the captured address including responsive to the compared values providing a command stream control for the captured address to ensure that a row hammer limit is not reached, wherein providing the selected row hammer avoidance action for the captured address includes holding mainline activates over an address range of the captured address, generating dummy read cycles for the captured address and said command stream control holding mainline read and write activates until at least one dummy read cycle is generated, eliminating row hammering effect and then allowing mainline read and write to activate.

2. The system as recited in claim 1 includes control code stored on a computer readable medium, and wherein said memory controller uses said control code for implementing row hammer avoidance.

3. The system as recited in claim 1 wherein said monitor and control logic providing the selected row hammer avoidance action for the captured address includes said monitor and control logic triggering scrub operations over an address range of the captured address based on the programmable threshold value.

4. The system as recited in claim 1 wherein said monitor and control logic includes an address capture register for storing the captured address.

5. The system as recited in claim 1 wherein said monitor and control logic includes a read cycle generator for generating one or more dummy read cycles for the captured address to eliminate hammering effect.

6. The system as recited in claim 1 wherein said monitor and control logic includes a command stream control for the captured address to trigger scrub operations.