Dual gate memory devices

• US 10,497,415 B2
• Filed: 01/08/2018
• Issued: 12/03/2019
• Est. Priority Date: 01/08/2018
• Status: Active Grant

• Current Assignee: Integrated Silicon Solution Incorporated (Uphill Investment Co.)
• Original Assignee: Spin Memory, Inc.
• Inventors: Kim, Kuk-Hwan, Sharma, Gian, Levi, Amitay
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): Techane, Muna A
• Application Number:
  US15/865,144
• Publication Number:
  US 20190214069A1
• Time in Patent Office: 694 Days
• Field of Search: 365158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1653 Address circuits or decoders
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5671 using charge trapping in an insulator
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type

Abstract

The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.

Claims

1. A memory device, comprising:

a current selector component, including;

a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store a first charge; and

a second charge storage device coupled in parallel with the first charge storage device, the second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store a second charge; and

a magnetic memory component electrically coupled to the current selector component; and

control circuitry coupled to first gate and the second gate of the current selector component and configured to govern operation of the current selector component, including;

enabling a read operation on the magnetic memory component by selectively enabling the first charge storage device to cause the current selector component to supply a first current to the magnetic memory component, the first current corresponding to the first charge; and

enabling a write operation on the magnetic memory component by selectively enabling the first charge storage device and/or the second charge storage device to cause the current selector component to supply a second current, greater than the first current, to the magnetic memory component.

2. The memory device of claim 1, wherein the first charge storage device comprises a transistor;

and

wherein the first gate comprises a floating gate configured to store the first charge.

3. The memory device of claim 1, wherein the first charge storage device comprises a transistor;

and

wherein the first gate comprises a charge trap configured to store the first charge.

4. The memory device of claim 3, wherein the first charge storage device is configured to:

store the first charge on a drain-side of the first gate; and

store a third charge on a source-side of the first gate.

5. The memory device of claim 1, wherein a channel of the first charge storage device is electrically-insulated from a channel of the second charge storage device.

6. The memory device of claim 1, wherein a channel doping of the first charge storage device is distinct from a channel doping of the second charge storage device.

7. The memory device of claim 1, wherein a work function of the first charge storage device is distinct from a work function of the second charge storage device.

8. The memory device of claim 1, further comprising a bitline;

and

wherein a first terminal of the first charge storage device and a first terminal of the second charge storage device are each coupled to the bitline via the magnetic memory component.

9. The memory device of claim 1, further comprising a source line;

and

wherein a second terminal of the first charge storage device and a second terminal of the second charge storage device are each coupled to the source line.

10. The memory device of claim 1, further comprising a first wordline and a second wordline;

and

wherein the first gate is coupled to the first wordline and the second gate is coupled to the second wordline.

11. The memory device of claim 1, wherein the first charge storage device comprises an N-channel device, a P-channel device, or a CMOS device.