Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on power supply voltage detection circuits

• US 10,497,430 B2
• Filed: 05/05/2017
• Issued: 12/03/2019
• Est. Priority Date: 06/22/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Siddique, Mushfique
• Application Number:
  US15/587,911
• Publication Number:
  US 20170372774A1
• Time in Patent Office: 942 Days
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor device powered by a first power supply potential, can include a voltage detector circuit coupled to receive the first power supply potential and configured to provide at least one voltage window signal, the at least one voltage window signal indicating a predetermined voltage window in which the first power supply potential is located; an assist control circuit configured to provide at least one assist signal in response to the at least one voltage window signal; wherein the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell, as compared to the read or write operations without the at least one assist signal.

Claims

1. A semiconductor device, comprising:

the semiconductor device powered by a first power supply potential, the first power supply potential being within one of a plurality of different voltage windows, each voltage window covering a different predetermined voltage range;

a voltage detector circuit coupled to receive the first power supply potential and configured to provide at least one voltage window signal, the at least one voltage window signal indicating the voltage window in which the first power supply potential is located;

an assist control circuit configured to provide at least one assist signal in response to the at least one voltage window signal;

a voltage window latch circuit coupled to receive the at least one voltage window signal and configured to provide at least one latched voltage window signal; and

a voltage window change detector circuit coupled to receive the at least one voltage window signal and configured to provide a voltage change detection signal in response to the at least one voltage window signal changing from a first logic level to a second logic level;

wherein

the at least one assist signal alters a read operation or a write operation to a static random access memory (SRAM) cell, as compared to the read or write operation to the SRAM cell without the at least one assist signal, and

the assist control circuit receives the at least one latched voltage window signal.

2. The semiconductor device of claim 1, further including:

a latch control circuit coupled to receive the voltage change detection signal and provide a voltage latch signal; and

the voltage window latch circuit is configured to latch the at least one voltage window signal in response to the voltage latch signal, and to provide the at least one latched voltage window signal.

3. The semiconductor device of claim 2, wherein:

the latch control circuit is coupled to receive an active signal and configured to provide the voltage latch signal in response to the active signal;

wherein

the active signal indicates the semiconductor device is in a standby mode of operation.

4. The semiconductor device of claim 2, wherein:

the voltage latch signal is a pulse signal having a predetermined pulse width.

5. The semiconductor device of claim 4, wherein:

the latch control circuit includes a latch circuit configured to be set in response to the voltage change detection signal and reset in response to the voltage latch signal.