Semiconductor device having electrically floating body transistor, semiconductor device having both volatile and non-volatile functionality and method of operating
First Claim
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1. An integrated circuit comprising:
- a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising;
a substrate;
a floating body region exposed at a surface of said substrate and configured to store volatile memory;
a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate;
a select gate positioned adjacent said substrate and said floating gate;
wherein said floating gate is configured to receive transfer of data stored by the volatile memory; and
a control circuit configured to perform operations on said memory array.
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Abstract
A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.
285 Citations
15 Claims
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1. An integrated circuit comprising:
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a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising; a substrate; a floating body region exposed at a surface of said substrate and configured to store volatile memory; a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; a select gate positioned adjacent said substrate and said floating gate; wherein said floating gate is configured to receive transfer of data stored by the volatile memory; and a control circuit configured to perform operations on said memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a plurality of rows and a plurality of columns, each said semiconductor memory cell comprising; a substrate; a floating body region configured to store volatile memory; a buried layer buried in a bottom portion of said substrate, said buried layer having a conductivity type different from a conductivity type of said floating body region; a stacked gate nonvolatile memory comprising a floating gate adjacent said substrate and a control gate adjacent said floating gate such that said floating gate is positioned between said control gate and said substrate; a select gate positioned adjacent said substrate and said floating gate; wherein applying a bias to said buried layer results in at least two stable floating body region charge levels; wherein said buried layer is commonly connected to at least two of said memory cells; and a control circuit configured to perform operations on said memory array. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification