Method of manufacturing a semiconductor device and a semiconductor device

• US 10,497,624 B2
• Filed: 03/29/2018
• Issued: 12/03/2019
• Est. Priority Date: 09/29/2017
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Shao-Ming, Lee, Tung Ying, Yun, Wei-Sheng, Yang, Fu-Hsiang
• Primary Examiner(s): Tran, Minh Loan
• Application Number:
  US15/940,329
• Publication Number:
  US 20190103317A1
• Time in Patent Office: 614 Days
• Field of Search: None
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/068 comprising a junction
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 : with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78618 : characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/78687 : with a multilayer structure or superlattice structure
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a first semiconductor layer having a first composition over a semiconductor substrate;

forming a second semiconductor layer having a second composition over the first semiconductor layer;

forming another first semiconductor layer having the first composition over the second semiconductor layer;

forming a third semiconductor layer having a third composition over the another first semiconductor layer;

patterning the first semiconductor layers, second semiconductor layer, and third semiconductor layer to form a fin structure;

removing a portion of the third semiconductor layer thereby forming a nanowire comprising the second semiconductor layer; and

forming a conductive material surrounding the nanowire,

wherein the first semiconductor layers, second semiconductor layer, and third semiconductor layer comprise different materials.

2. The method according to claim 1, wherein a stack of alternating first semiconductor layers, second semiconductor layers, another first semiconductor layers, and third semiconductor layers is formed by repeating, in order, forming the first semiconductor layer, forming the second semiconductor layer, forming the another first semiconductor layer, and forming the third semiconductor layer.

3. The method according to claim 1, further comprising:

forming a sacrificial gate structure over the fin structure before the removing a portion of the third semiconductor layer.

4. The method according to claim 3, further comprising:

removing a portion of the fin structure, which is not covered by the sacrificial gate structure, before the removing a portion of the third semiconductor layer, thereby forming a source/drain space.

5. The method according to claim 4, further comprising forming source/drain regions in the source/drain space.

6. The method according to claim 1, further comprising removing a portion of the semiconductor substrate when forming the nanowire.

7. The method according to claim 1, wherein the third semiconductor layer and the semiconductor substrate are formed of a same material.

8. The method according to claim 7, wherein the same material is silicon.

9. The method according to claim 1, wherein the first semiconductor material is Si_1-xGe_x, and the second semiconductor material is Si_1-yGe_y, wherein x>

y.

10. A method of manufacturing a semiconductor device, comprising:

forming a fin structure over a semiconductor substrate in which first semiconductor layers A, second semiconductor layers B, and third semiconductor layers C are stacked in a repeating sequence ABAC,

wherein the first semiconductor, second semiconductor, and third semiconductor layers comprise different materials;

forming a sacrificial gate structure defining a gate region over the fin structure;

removing the third semiconductor layers from source/drain regions of the fin structure, which are not covered by the sacrificial gate structure;

forming source/drain epitaxial layers in the source/drain regions;

removing the sacrificial gate structure;

removing the third semiconductor layers from the gate region; and

forming a gate electrode structure in the gate region, wherein the gate electrode structure wraps around the first and second semiconductor layers.

11. The method according to claim 10, further comprising removing a portion of the semiconductor substrate when removing the third semiconductor layers.

12. The method according to claim 10, wherein the third semiconductor layer and the semiconductor substrate are formed of a same material.

13. The method according to claim 12, wherein the same material is a Group IV element.

14. The method according to claim 10, wherein the first semiconductor material is Si_1-xGe_x, the second semiconductor material is Si_1-yGe_y, and third semiconductor material is silicon, wherein x>

y.

15. The method according to claim 14, wherein 0.3≤

x≤

0.9 and 0.1≤

y≤

0.5.

16. The method according to 15, wherein the first and second semiconductor layers are epitaxially formed and during the epitaxial operation the Ge concentration is increased to form the first semiconductor layer and the Ge concentration is reduced to form the second semiconductor layer.

17. The method according to claim 10, wherein a thickness of the second semiconductor layer is greater than a thickness of the third semiconductor layer.

18. A method of manufacturing a semiconductor device, comprising:

forming a first fin structure and a second fin structure, wherein in both the first fin structure and the second fin structure first semiconductor layers and second semiconductor layers are alternately stacked;

forming a first sacrificial gate structure over the first fin structure and a second sacrificial gate structure over the second fin structure;

forming a first protective layer over the second fin structure and the second sacrificial gate structure;

removing the first semiconductor layers in a source/drain region of the first fin structure, which is not covered by the first sacrificial gate structure, thereby forming a first source/drain space;

forming a first source/drain epitaxial layer in the first source/drain space, thereby forming a first structure;

forming a second protective layer over the first fin structure and the first sacrificial gate structure;

removing the second semiconductor layers in a source/drain region of the second fin structure, which is not covered by the second sacrificial gate structure, thereby forming a second source/drain space;

forming a second source/drain epitaxial layer in the second source/drain space, thereby forming a second structure;

removing the first sacrificial gate structure and the first semiconductor layer in the first gate region to form a first gate space;

removing the second sacrificial gate structure and the second semiconductor layer in the second gate region to form a second gate space;

forming first and second gate electrode structures in the first and second gate spaces, respectively,

wherein the first semiconductor layer comprises a first sublayer and second sublayers disposed on opposing sides of the first sublayer, the first sublayer formed of an alloy comprising a first Group IV element and a second Group IV element, and the second sublayers formed of an alloy comprising the first Group IV element and the second Group IV element, the amounts of the first Group IV element and second Group IV element being different in the first sublayer and the second sublayers.

19. The method of claim 18, wherein the first Group IV element is Si and the second Group IV element is Ge.

20. The method of claim 19, wherein the composition of the first sublayer is Si_1-yGe_y, where 0.1≤

y≤

0.5, and the composition of the second sublayers is Si_1-xGe_x, where 0.3≤

x≤

0.9.