Semiconductor device and manufacturing method thereof

• US 10,497,650 B2
• Filed: 04/13/2017
• Issued: 12/03/2019
• Est. Priority Date: 04/13/2017
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Kim, Soo Hyun, Na, Jae Min, Kim, Dae Gon, Hwang, Tae Kyung, Lim, Kwang Mo Chris, Park, SungSun, Kim, KyeRyung
• Primary Examiner(s): Garber, Charles D
• Assistant Examiner(s): Sabur, Alia
• Application Number:
  US15/487,024
• Publication Number:
  US 20180301420A1
• Time in Patent Office: 964 Days
• CPC Class Codes: H01L 21/4885 Wire-like parts or pins wire ball formation B23K20/00; methods related to connecting semiconductor or other solid state bodies H01L24/00
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device antennas per se H01Q
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05657 Cobalt [Co] as principal constituent
• CPC Class Codes: H01L 2224/05663 the principal constituent melting at a temperature of greater than 1550°C
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/0567 Zirconium [Zr] as principal constituent
• CPC Class Codes: H01L 2224/05671 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05676 : Ruthenium [Ru] as principal constituent
• CPC Class Codes: H01L 2224/0568 : Molybdenum [Mo] as principal constituent
• CPC Class Codes: H01L 2224/05683 : Rhenium [Re] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05693 : with a principal constituent of the material being a solid not provided for in groups H01L2224/056 - H01L2224/05691, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/0579 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/05794 : with a principal constituent of the material being a liquid not provided for in groups H01L2224/057 - H01L2224/05791
• CPC Class Codes: H01L 2224/05839 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05886 : with a principal constituent of the material being a non metallic, non metalloid inorganic material
• CPC Class Codes: H01L 2224/05893 : with a principal constituent of the material being a solid not provided for in groups H01L2224/058 - H01L2224/05891, e.g. allotropes of carbon, fullerene, graphite, carbon-nanotubes, diamond
• CPC Class Codes: H01L 2224/06181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/11 : Manufacturing methods
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16237 : the bump connector connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29299 : Base material
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 : Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49173 : Radial fan-out arrangements
• CPC Class Codes: H01L 2224/73257 : Bump and wire connectors
• CPC Class Codes: H01L 2224/78301 : Capillary
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81203 : Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
• CPC Class Codes: H01L 2224/81399 : Material
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/85399 : Material
• CPC Class Codes: H01L 2224/92227 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/50 : for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/66 : High-frequency adaptations
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/46 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/053 : Oxides composed of metals from groups of the periodic table
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device having an EMI shield layer and/or EMI shielding wires, and a manufacturing method thereof, are provided. In an example embodiment, the semiconductor device includes a semiconductor die, an EMI shield layer shielding the semiconductor die, and an encapsulating portion encapsulating the EMI shield layer. In another example embodiment, the semiconductor device further includes EMI shielding wires extending from the EMI shield layer and shielding the semiconductor die.

Claims

1. A semiconductor device comprising:

a semiconductor die including a first surface, a second surface opposite to the first surface, a third surface formed between the first surface and the second surface, and a plurality of interconnection structures formed on the second surface;

an EMI shield layer contacting the first surface and the third surface of the semiconductor die;

a substrate electrically connected to the plurality of interconnection structures of the semiconductor die;

an encapsulating portion encapsulating the EMI shield layer and the substrate, the encapsulating portion comprising a mold material adhered to the EMI shield layer;

another semiconductor die horizontally spaced apart from the semiconductor die; and

wherein the EMI shield layer fills a gap between the semiconductor die and the other semiconductor die with EMI shielding material to a level that at least surpasses the second surface of the semiconductor die.

2. The semiconductor device of claim 1, wherein the semiconductor die comprises:

a contact pad electrically connected to an interconnection structure of the plurality of interconnection structures; and

a ground circuit pattern electrically connecting the contact pad and the EMI shield layer.

3. The semiconductor device of claim 1, where in the EMI shield layer comprises a material selected from a conductive polymer, a conductive ink, a conductive paste, and a conductive foil.

4. The semiconductor device of claim 1, further comprising an underfill that fills a gap between the semiconductor die and the substrate.

5. The semiconductor device of claim 1, wherein the EMI shield layer comprises a non-sputtered EMI shield layer.

6. The semiconductor device of claim 1, wherein the EMI shield layer comprises a copper foil.

7. The semiconductor device of claim 1, wherein the EMI shield layer comprises a spin-coated EMI shield layer.

8. The semiconductor device of claim 1, wherein the EMI shield layer comprises a jet-printed EMI shield layer.

9. A semiconductor device comprising:

a semiconductor die including a first surface, a second surface opposite to the first surface, a third surface formed between the first surface and the second surface, and a plurality of interconnection structures formed on the second surface;

a non-sputtered EMI shield layer comprising an upper surface and a lower surface opposite the upper surface, wherein the lower surface faces the first surface of the semiconductor die;

a plurality of EMI shielding wires positioned about the third surface of the semiconductor die, the plurality of EMI shielding wires physically and electrically connected to the upper surface of the non-sputtered EMI shield layer;

a substrate comprising a first substrate surface, a second substrate surface opposite the first substrate surface, conductive traces, and a ground circuit pattern exposed on the first substrate surface, wherein the plurality of interconnection structures of the semiconductor die are physically connected to the conductive traces exposed on the first substrate surface, and wherein the plurality of EMI shielding wires are physically and electrically connected to the ground circuit pattern exposed on the first substrate surface; and

an encapsulating portion encapsulating and directly contacting the non-sputtered EMI shield layer, the EMI shielding wires, and the first substrate surface.

10. The semiconductor device of claim 9, wherein the non-sputtered EMI shield layer comprises a material selected from a conductive polymer, a conductive ink, a conductive paste, and a conductive foil.

11. The semiconductor device of claim 9, wherein the plurality of EMI shielding wires traverse and inductively shield the third surface of the semiconductor die.

12. The semiconductor device of claim 11, wherein the plurality of EMI shielding wires are spaced apart from the third surface of the semiconductor die.

13. The semiconductor device of claim 9, wherein:

the non-sputtered EMI shield layer has a rectangular shape with four sides; and

the plurality of EMI shielding wires are arranged along the four sides.

14. A semiconductor device comprising:

a semiconductor die including a first surface, a second surface opposite to the first surface, a third surface formed between the first surface and the second surface, and a plurality of interconnection structures formed on the second surface;

a substrate electrically connected to the plurality of interconnection structures of the semiconductor die;

an encapsulating portion encapsulating the first surface of the semiconductor die and the third surface of the semiconductor die, the encapsulating portion comprising a first surface over the first surface of the semiconductor die and a side surface between the first surface of the encapsulating portion and the substrate; and

an EMI shield layer comprising a first surface on the side surface of the encapsulating portion and a second surface opposite the first surface of the EMI shield layer, wherein the second surface of the EMI shield layer slants from the substrate toward the semiconductor die and the first surface of the encapsulating portion, and wherein at least a portion of the first surface of the encapsulating portion is exposed by the EMI shield layer.

15. The semiconductor device of claim 14, wherein the substrate further includes an antenna pattern that traverses the EMI shield layer.

16. The semiconductor device of claim 14, wherein the EMI shield layer comprises a non-sputtered EMI shield layer.

17. The semiconductor device of claim 15, wherein the EMI shield layer shields the semiconductor device from the antenna pattern.

18. The semiconductor device of claim 15, wherein the encapsulating portion further encapsulates the antenna pattern.

19. The semiconductor device of claim 15, wherein the antenna pattern extends beyond the encapsulating portion.