Semiconductor circuit and semiconductor device

• US 10,497,698 B2
• Filed: 06/10/2016
• Issued: 12/03/2019
• Est. Priority Date: 06/10/2016
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Yoshino, Manabu
• Primary Examiner(s): Dang, Phuc T
• Application Number:
  US16/090,917
• Publication Number:
  US 20190109130A1
• Time in Patent Office: 1,271 Days
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 27/06 including a plurality of individual components in a non-repetitive configuration
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/7817 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H03F 3/34 DC amplifiers in which all stages are DC-coupled H03F3/45 takes precedence
• CPC Class Codes: H03K 19/0185 using field effect transistors only
• CPC Class Codes: H03K 3/037 Bistable circuits

Abstract

An object is to provide a technique for enhancing the breakdown voltage of a semiconductor device. A semiconductor circuit includes a first resistor, a second resistor, a third resistor, a MOSFET, and an inverter. The first resistor, the second resistor, and the third resistor are connected in series between a power supply and a ground corresponding to the reference voltage of a low-side circuit. The MOSFET is connected to the third resistor in parallel between the second resistor and the ground, and has a gate electrically connected to the low-side circuit. The inverter is electrically connected between a connection point and the high-side circuit, the connection point being located between the first resistor and the second resistor.

Claims

1. A semiconductor circuit electrically connected between a low-side circuit and a high-side circuit whose reference voltage is higher than a reference voltage of the low-side circuit, the semiconductor circuit comprising:

a first resistor, a second resistor, and a third resistor that are connected in series between a power supply and a ground corresponding to the reference voltage of the low-side circuit, and are arranged in this order from the power supply toward the ground;

a MOSFET connected to the third resistor in parallel between the second resistor and the ground, and comprising a gate electrically connected to the low-side circuit; and

an inverter electrically connected between a connection point and the high-side circuit, the connection point being positioned between the first resistor and the second resistor, wherein

the semiconductor circuit satisfies the following expression (2) when a voltage of the power supply is a value V1, when a power supply voltage of the high-side circuit is a value V3, the power supply voltage corresponding to an absolute value of a difference between the voltage of the power supply and the reference voltage of the high-side circuit, when the first resistor has a value R1, when the second resistor has a value R2, when the third resistor has a value R3, when a combined resistance of an on-resistance of the MOSFET combined with the third resistor is a value R_CO, and when a threshold voltage of the inverter is a value Vinvth;

2. A semiconductor device comprising

a substrate comprising a main surface on which the semiconductor circuit according to claim 1 is disposed, wherein

a high-side-circuit region in which the high-side circuit is disposed is defined in a region on the main surface of the substrate other than a region in which the MOSFET of the semiconductor circuit is disposed,

on the main surface of the substrate,

a first insulator surrounding an outer periphery of the high-side-circuit region is disposed, and

a drain and a source of the MOSFET of the semiconductor circuit are disposed so as to be spaced away from each other,

the first resistor comprises a polysilicon resistor disposed within the high-side-circuit region in plan view, and

the third resistor comprises a polysilicon resistor comprising one end connected to the drain and another end connected to the source, and having a spiral shape.

3. The semiconductor device according to claim 2, wherein the second resistor comprises a polysilicon resistor, in plan view, provided so as to surround the outer periphery of the high-side-circuit region and having a spiral shape.

4. The semiconductor device according to claim 2, wherein

the substrate comprises an SOI layer comprising the main surface, and

the second resistor comprises a polysilicon resistor buried inside the first insulator so as to surround the outer periphery of the high-side-circuit region, and having a spiral shape, the SOI layer having a spiral shape, or the SOI layer with an impurity diffused in a spiral shape.

5. The semiconductor device according to claim 2, wherein

a low-side-circuit region in which the low-side circuit is disposed is defined in a region on the main surface of the substrate other than the high-side-circuit region, and

the second resistor comprises a polysilicon resistor, in plan view, disposed within the low-side-circuit region and having an accordion shape or a polygonal-line shape.

6. The semiconductor device according to claim 2, wherein

the substrate comprises an SOI layer comprising the main surface,

a low-side-circuit region in which the low-side circuit and a second insulator are disposed is defined in a region on the main surface of the substrate other than the high-side-circuit region, and

the second resistor comprises a polysilicon resistor buried inside the second insulator and having an accordion shape or a polygonal-line shape, the SOI layer having an accordion shape or a polygonal-line shape, or the SOI layer with an impurity diffused in an accordion shape or a polygonal-line shape.

7. The semiconductor device according to claim 2, wherein the second resistor comprises a polysilicon resistor, in plan view, disposed within the high-side-circuit region and having an according shape or a polygonal-line shape.

8. The semiconductor device according to claim 2, wherein

the substrate comprises an SOI layer comprising the main surface,

a second insulator is further disposed in the high-side-circuit region, and

the second resistor comprises a polysilicon resistor buried inside the second insulator and having an accordion shape or a polygonal-line shape, the SOI layer having an accordion shape or a polygonal-line shape, or the SOI layer with an impurity diffused in an accordion shape or a polygonal-line shape.