3D semiconductor memory device and structure
First Claim
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1. A semiconductor memory, comprising:
- a first memory cell comprising a first transistor;
a second memory cell comprising a second transistor;
a memory peripherals transistor, said memory peripherals transistor is atop said second transistor,wherein said second memory cell is above said first memory cell at a distance of less than 200 nm,wherein said memory peripherals transistor is part of a peripherals circuit controlling said memory, andwherein said second memory cell and said first memory cell have been processed following the same lithography step and accordingly are self-aligned; and
a copper-based connection layer disposed between said memory peripherals transistor and said second memory cell.
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Abstract
A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.
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7 Claims
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1. A semiconductor memory, comprising:
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a first memory cell comprising a first transistor; a second memory cell comprising a second transistor; a memory peripherals transistor, said memory peripherals transistor is atop said second transistor, wherein said second memory cell is above said first memory cell at a distance of less than 200 nm, wherein said memory peripherals transistor is part of a peripherals circuit controlling said memory, and wherein said second memory cell and said first memory cell have been processed following the same lithography step and accordingly are self-aligned; and a copper-based connection layer disposed between said memory peripherals transistor and said second memory cell. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification