Voltage sampler driver with enhanced high-frequency gain

• US 10,498,305 B2
• Filed: 06/19/2018
• Issued: 12/03/2019
• Est. Priority Date: 01/25/2016
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Tajalli, Armin
• Primary Examiner(s): Mottola, Steven J
• Application Number:
  US16/012,649
• Publication Number:
  US 20180302053A1
• Time in Patent Office: 532 Days
• Field of Search: 330252-254
• CPC Class Codes: H03F 2200/366 Multiple MOSFETs are coupled in parallel
• CPC Class Codes: H03F 2203/45022 One or more added resistors to the amplifying transistors in the differential amplifier
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45197 Pl types H03F3/45224, H03F3/45251 take precedence
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence
• CPC Class Codes: H03G 3/3089 Control of digital or coded signals
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/03133 with a non-recursive structure H04L25/03127 takes precedence
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection

Abstract

Methods and systems are described for receiving, at an input differential branch pair, a set of input signals, and responsively generating a first differential current, receiving, at an input of an offset voltage branch pair, an offset voltage control signal, and responsively generating a second differential current, supplementing a high-frequency component of the second differential current by injecting a high-pass filtered version of the set of input signals into the input of the offset voltage branch pair using a high-pass filter, and generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

Claims

1. An apparatus comprising:

a voltage sampler driver connected to a pair of output nodes, the voltage sampler driver configured to generate an output differential current through the pair of output nodes from at least a first and a second differential current, the voltage sampler driver comprising;

an input differential branch pair configured to receive a set of input signals corresponding to symbols of a codeword and to responsively generate the first differential current, the input differential branch pair comprising a first branch having a plurality of transistors connected in parallel to a first output node of the pair of output nodes, the plurality of transistors of the first branch configured to receive corresponding input signals of the set of input signals and to responsively generate a plurality of partial currents that are summed via the first output node to form a portion of the first differential current; and

an offset voltage branch pair, each branch of the offset voltage branch pair configured to receive (i) an offset voltage control signal and (ii) one or more input signals of the set of input signals via respective high-pass filtered inputs, each branch of the offset differential branch pair comprising one or more transistors configured to generate the second differential current having an offset correction component and a supplemented high-frequency component of the set of input signals; and

an amplifier stage connected to the voltage sampler driver, the amplifier stage configured to generate a differential output voltage on the pair of output nodes based on the output differential current.

2. The apparatus of claim 1, wherein the voltage sampler driver further comprises respective tail current sources, the respective tail current sources enabled according to transistors in the input differential branch pair and offset differential branch pair to generate the first and second differential currents.

3. The apparatus of claim 2, wherein the respective tail current sources are further periodically enabled according to an input clock signal.

4. The apparatus of claim 1, wherein the plurality of partial currents have magnitudes proportional to signal values of the corresponding input signals.

5. The apparatus of claim 1, wherein the amplifier stage comprises:

a pair of load resistors configured to generate the differential output voltage based on the output differential current; and

a pair of capacitors, each capacitor connected between one terminal of a corresponding load resistor and ground.

6. The apparatus of claim 5, wherein the pair of load resistors are tunable.

7. The apparatus of claim 6, wherein the amplifier stage further comprises an adjustable tail current source.

8. The apparatus of claim 7, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the load resistors is constant, and wherein the pair of load resistors and the adjustable tail current source have a bandwidth control input to adjust bandwidth.

9. The apparatus of claim 7, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the load resistors is not constant, the pair of load resistors and the adjustable tail current source having a power control input to adjust power consumption.

10. The apparatus of claim 6, wherein each tunable load resistor comprises a plurality of resistors in a parallel network, each resistor of the plurality having a corresponding switch connected between the resistor and a common node of the parallel network, and wherein each switch is configured to connect or disconnect the resistor from the parallel network based on a respective control signal.

11. A method comprising:

receiving, at an input differential branch pair connected to a pair of output nodes, a set of input signals, and responsively generating a first differential current, wherein a portion of the first differential current is generated using a plurality of transistors in a first branch of the input differential branch pair, the plurality of transistors receiving corresponding input signals of the set of input signals and responsively forming a plurality of partial currents that are summed via a first output node of the pair of output nodes;

receiving, at an input of an offset voltage branch pair connected to the pair of output nodes, (i) an offset voltage control signal and (ii) one or more input signals of the set of input signals via respective high-pass filtered inputs, and responsively generating a second differential current having an offset correction component and a supplemented high-frequency component of the received set of input signals; and

generating an output differential current based on the first and second differential currents using an amplifier stage connected to the input differential branch pair and the offset voltage branch pair.

12. The method of claim 11, wherein generating the first and second differential currents comprises enabling corresponding tail current sources for the input differential branch pair and the offset differential branch pair according to corresponding transistors in the input differential branch pair and the offset differential branch pair.

13. The method of claim 12, wherein the respective tail current sources are enabled according to an input clock signal provided to the corresponding transistors in the input differential branch pair and the offset differential branch pair.

14. The method of claim 11, wherein the plurality of partial currents have magnitudes proportional to the corresponding input signals of the set of input signals received at the plurality of transistors.

15. The method of claim 11, further comprising generating a differential output voltage by drawing the output differential current through a pair of load resistors, wherein each load resistor has a corresponding capacitor connected between one terminal of the load resistor and ground.

16. The method of claim 15, wherein the pair of load resistors are tunable.

17. The method of claim 16, wherein the amplifier stage further comprises an adjustable tail current source.

18. The method of claim 17, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the load resistors is constant, and wherein the method further comprises adjusting the pair of load resistors and the adjustable tail current source to adjust bandwidth.

19. The method of claim 17, wherein a product of a current magnitude of the adjustable tail current source and an impedance magnitude of one of the load resistors is not constant, and wherein the method further comprises adjusting the pair of load resistors and the adjustable tail current source to adjust power consumption.

20. The method of claim 16, wherein each tunable load resistor comprises a plurality of resistors in a parallel network, and wherein the method further comprises selectably enabling each resistor of the plurality of resistors according to a corresponding switch receiving a corresponding control signal.