On-chip TDDB degradation monitoring and failure early warning circuit for SoC
First Claim
1. An on-chip TDDB degradation monitoring and failure early warning circuit for SoC, comprising:
- a timing logic module (100), a control circuit module (200), a digital conversion module for TDDB performance degradation (300), an output selection module (400) and a counter module (500), wherein the counter module (500) includes a counter A and a counter B;
the digital conversion module for TDDB performance degradation (300) includes two same MOS transistor circuits including a first MOS transistor circuit and a second MOS transistor circuit;
the timing logic module (100) includes X, Y and CP signal input terminals and Q1 and Q0 output terminals, and the timing logic module is configured to output the Q1 and Q0 signals with a high or low level voltage to the control circuit module (200) under control of input X, Y and CP signals;
the control circuit module (200) is configured to convert the Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to the digital conversion module for TDDB performance degradation (300);
a MOS transistor of the first MOS transistor circuit is in a stress state of the supply voltage and a MOS transistor of the second MOS transistor circuit is in a non-stress state within the digital conversion module for TDDB performance degradation (300);
the first and the second MOS transistor circuits output a first and second frequency value to the output selection module (400) respectively, under control of the switch state control signal;
the output selection module (400) is configured to output the first frequency value from the digital conversion module for TDDB performance degradation (300) to the counter B for recording, or output the second frequency value from the digital conversion module for TDDB performance degradation to the counter A for recording; and
the counter module (500) is configured to determine a degradation level of TDDB performance by comparing the first frequency value with the second frequency value.
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Abstract
An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.
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Citations
10 Claims
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1. An on-chip TDDB degradation monitoring and failure early warning circuit for SoC, comprising:
- a timing logic module (100), a control circuit module (200), a digital conversion module for TDDB performance degradation (300), an output selection module (400) and a counter module (500), wherein the counter module (500) includes a counter A and a counter B;
the digital conversion module for TDDB performance degradation (300) includes two same MOS transistor circuits including a first MOS transistor circuit and a second MOS transistor circuit;the timing logic module (100) includes X, Y and CP signal input terminals and Q1 and Q0 output terminals, and the timing logic module is configured to output the Q1 and Q0 signals with a high or low level voltage to the control circuit module (200) under control of input X, Y and CP signals; the control circuit module (200) is configured to convert the Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to the digital conversion module for TDDB performance degradation (300); a MOS transistor of the first MOS transistor circuit is in a stress state of the supply voltage and a MOS transistor of the second MOS transistor circuit is in a non-stress state within the digital conversion module for TDDB performance degradation (300);
the first and the second MOS transistor circuits output a first and second frequency value to the output selection module (400) respectively, under control of the switch state control signal;the output selection module (400) is configured to output the first frequency value from the digital conversion module for TDDB performance degradation (300) to the counter B for recording, or output the second frequency value from the digital conversion module for TDDB performance degradation to the counter A for recording; and the counter module (500) is configured to determine a degradation level of TDDB performance by comparing the first frequency value with the second frequency value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- a timing logic module (100), a control circuit module (200), a digital conversion module for TDDB performance degradation (300), an output selection module (400) and a counter module (500), wherein the counter module (500) includes a counter A and a counter B;
Specification