On-chip TDDB degradation monitoring and failure early warning circuit for SoC

• US 10,503,578 B2
• Filed: 11/29/2016
• Issued: 12/10/2019
• Est. Priority Date: 08/30/2016
• Status: Active Grant

• Current Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
• Original Assignee: Fifth Electronics Research Institute of Ministry of Industry and Information Technology
• Inventors: Chen, Yiqiang, Lei, Dengyun, En, Yunfei, Fang, Wenxiao, Hao, Lichao, Huang, Yun, Hou, Bo, Lu, Yudong
• Primary Examiner(s): Chaudry, Mujtaba M
• Application Number:
  US15/556,751
• Publication Number:
  US 20190205196A1
• Time in Patent Office: 1,106 Days
• Field of Search: None
• CPC Class Codes: G01R 31/14 Circuits therefor , e.g. for generating test voltages, sensing circuits G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/008 Reliability or availability analysis
• CPC Class Codes: G06F 11/0736 in functional embedded systems, i.e. in a data processing system designed as a combination of hardware and software dedicated to performing a certain function testing or monitoring of automated control systems G05B23/02
• CPC Class Codes: G06F 11/0754 by exceeding limits
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 11/3013 where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems testing or monitoring of control systems or parts thereof G05B23/02
• CPC Class Codes: G06F 11/3495 for systems

Abstract

An on-chip TDDB degradation monitoring and failure early warning circuit for SoC. A control circuit module converts Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to a digital conversion module for TDDB performance degradation. A MOS transistor of a first MOS transistor circuit within the digital conversion module for TDDB performance degradation is in a stress state of a supply voltage, and a MOS transistor of a second MOS transistor circuit is in a non-stress state. The first and second MOS transistor circuits output a first frequency value and a second frequency value to the output selection module. The output selection module outputs the first frequency value from the digital conversion module to the counter B for recording, or outputs the second frequency value to the counter A for recording. The counter module determines the degradation level of TDDB performance.

Claims

1. An on-chip TDDB degradation monitoring and failure early warning circuit for SoC, comprising:

a timing logic module (100), a control circuit module (200), a digital conversion module for TDDB performance degradation (300), an output selection module (400) and a counter module (500), wherein the counter module (500) includes a counter A and a counter B;

the digital conversion module for TDDB performance degradation (300) includes two same MOS transistor circuits including a first MOS transistor circuit and a second MOS transistor circuit;

the timing logic module (100) includes X, Y and CP signal input terminals and Q1 and Q0 output terminals, and the timing logic module is configured to output the Q1 and Q0 signals with a high or low level voltage to the control circuit module (200) under control of input X, Y and CP signals;

the control circuit module (200) is configured to convert the Q1 and Q0 signals into a switch state control signal and outputs the switch state control signal to the digital conversion module for TDDB performance degradation (300);

a MOS transistor of the first MOS transistor circuit is in a stress state of the supply voltage and a MOS transistor of the second MOS transistor circuit is in a non-stress state within the digital conversion module for TDDB performance degradation (300);

the first and the second MOS transistor circuits output a first and second frequency value to the output selection module (400) respectively, under control of the switch state control signal;

the output selection module (400) is configured to output the first frequency value from the digital conversion module for TDDB performance degradation (300) to the counter B for recording, or output the second frequency value from the digital conversion module for TDDB performance degradation to the counter A for recording; and

the counter module (500) is configured to determine a degradation level of TDDB performance by comparing the first frequency value with the second frequency value.

2. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein the Q1 and Q0 signals correspond to a state selected from an S0 state, an S1 state, an S2 state, and an S3 state;

when the Q1 output terminal is “

0” and

the Q0 output terminal is “

0”

, the S0 state is a corresponding state;

when the Q1 output terminal is “

0” and

the Q0 output terminal is “

1”

, the S1 state is a corresponding state;

when the Q1 output terminal is “

1” and

the Q0 output terminal is “

0”

, the S2 state is a corresponding state; and

when the Q1 output terminal is “

1” and

the Q0 output terminal is “

1”

, the S3 state is a corresponding state.

3. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 2, wherein when the timing logic module (100) is in the S3 state, the timing logic module (100) is switched to the S2 state under any level voltage input from the X and Y input terminals;

when the timing logic module (100) is in the S2 state and a combination of signals input into the X and Y input terminals is any one of “

00”

, “

01”

, and “

10”

, the timing logic module (100) continues to be in the S2 state;

when the timing logic module (100) is in the S2 state and the combination of signals input into the X and Y input terminals is “

11”

, the timing logic module (100) is switched to the S0 state from the S2 state;

when the timing logic module (100) is in the S0 state and the combination of signals input into the X and Y input terminals is “

01”

, the timing logic module (100) continues to be in the S2 state;

when the timing logic module (100) is in the S0 state and the combination of signals input into the X and Y input terminals is “

00”

or “

10”

, the timing logic module (100) is switched to the S2 state from the S0 state;

when the timing logic module (100) is in the S0 state and the combination of signals input into the X and Y input terminals is “

11”

, the timing logic module (100) is switched to the S1 state from the S0 state;

when the timing logic module (100) is in the S1 state and the combination of signals input into the X and Y input terminals is “

01”

, the timing logic module (100) continues to be in the S1 state; and

when the timing logic module (100) is in the S1 state and the combination of signals input into the X and Y input terminals is “

00”

, “

10”

or “

11”

, the timing logic module (100) is switched to the S2 state from the S1 state.

4. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein the control circuit module (200) includes:

a first input terminal (201), a second input terminal (202), a first inverter (203), a first AND gate (204), a second inverter (205), a third inverter (206), a first junction (207), and a second junction (208), a second AND gate (209), a third AND gate (210), a fourth AND gate (211), a fifth AND gate (212), a sixth AND gate (216), a seventh AND gate (217), an eighth AND gate (218), a ninth AND gate (219), a first output terminal (220), a second output terminal (221), a third output terminal (222), a fourth output terminal (223), and a fifth output terminal (224);

an input terminal of the first inverter (203) is connected to the first input terminal (201), and an output terminal of the first inverter (203) is connected to the second junction (208);

one input terminal of the first AND gate (204) is connected to the first input terminal (201), another input terminal of the first AND gate (204) is connected to the second input terminal (202), and an output terminal of the first AND gate (204) is connected to an input terminal of the third inverter (206);

an input terminal of the second inverter (205) is connected to the second input terminal (202), and an output terminal of the second inverter (205) is connected to the first junction (207);

one input terminal of the second AND gate (209) is connected to the first input terminal (201), and another input terminal of the second AND gate (209) is connected to the first junction (207);

one input terminal of the third AND gate (210) is connected to the first junction (207), and another input terminal of the third AND gate (210) is connected to an output terminal of the first inverter (203);

one input terminal of the fourth AND gate (211) is connected to the second junction (208), and another input terminal of the fourth AND gate (211) is connected to the second input terminal (202);

one input terminal of the fifth AND gate (212) is connected to the second input terminal (202), and another input terminal of the fifth AND gate (212) grounded,

one input terminal of the sixth AND gate (216) is connected to an output terminal of the second AND gate (209), and another input terminal of the sixth AND gate (216) is connected to the fifth output terminal (224);

one input terminal of the seventh AND gate (217) is connected to an output terminal of the third AND gate (210), and another input terminal of the seventh AND gate (217) is connected to a fifth output terminal (224);

one input terminal of the eighth AND gate (218) is connected to an output terminal of the AND gate (211), and another input terminal of the eighth AND gate (218) is connected to the fifth output terminal (224); and

one input terminal of the AND gate (219) is connected to an output terminal of the AND gate (212), and another input terminal of the AND gate (219) is connected to the fifth output terminal (224).

5. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein the digital conversion module for TDDB performance degradation (300) includes:

a third input terminal (301), a tenth AND gate (302),

a first switch (303), a third junction (304), a second switch (305), a third switch (306), a first NMOS transistor (307), a fourth switch (308), a fourth junction (309), a fifth switch (310), a sixth switch (311), a second NMOS transistor (312), a fifth junction (313), a first inverter (314),

a seventh switch (315), a sixth junction (316), an eighth switch (317), a ninth switch (318), a third NMOS transistor (319), a tenth switch (320), a seventh junction (321), an eleventh switch (322), a twelfth switch (323), a fourth NMOS (324), an eighth junction (325), a second inverter (326),

a thirteenth switch (327), a ninth junction (328), a fourteenth switch (329), a fifteenth switch (330), a fifth NMOS transistor (331), a sixteenth switch (332), a tenth junction (333), a seventeenth switch (334), an eighteenth switch (335), a sixth NMOS (336), an eleventh junction (337), a third inverter (338), and

a sixth output terminal (339),

wherein the third switch (306), the ninth switch (318) and the fifteenth switch (330) are connected to the first output terminal (220) respectively;

the first switch (303), the second switch (305), the seventh switch (315), the eighth switch (317), the thirteenth switch (327), and the fourteenth switch (329) are connected to the second output terminal (221) respectively;

the fourth switch (308), the fifth switch (310), the tenth switch (320), the eleventh switch (322), the sixteenth switch (332) and the seventeenth switch (334) are connected to the third output terminal (222) respectively;

the sixth switch (311), the twelfth switch (323) and the eighteenth switch (335) are connected to the fourth output terminal (223) respectively;

the fifth output terminal (224) is connected to the third input terminal (301);

one input terminal of the tenth AND gate (302) is connected to the third input terminal (301), another input terminal of the tenth AND gate (302) is connected to the sixth output terminal (339), and an output terminal of the tenth AND gate (302) is connected to the first switch (303);

one end of the first switch (303) is connected to an output terminal of the tenth AND gate (302), and another end of the first switch (303) is connected to the third junction (304);

one end of the third switch (306) is connected to the power supply VDD, and another end of the third switch (306) is connected to the third junction (304);

one end of the second switch (305) is connected to the third junction (304), and another end of the second switch (305) is connected to the fifth junction (313);

a gate terminal of the first NMOS transistor (307) is connected to the third junction (304), and a source terminal and a drain terminal of the first NMOS transistor (307) are grounded respectively;

one end of the fourth switch (308) is connected to an output terminal of the tenth AND gate (302), and another end of the fourth switch (308) is connected to the fourth junction (309);

one end of the sixth switch (311) is connected to the power supply VDD, and another end of the sixth switch (311) is connected to the fourth junction (309);

one end of the fifth switch (310) is connected to the fourth junction (309), and another end of the fifth switch (310) is connected to the fifth junction (313);

a gate terminal of the second NMOS transistor (312) is connected to the fourth junction (309), and a source terminal and a drain terminal of the second NMOS transistor (312) are grounded respectively;

an input terminal of the first inverter (314) is connected to the fifth junction (313), and an output terminal is connected to the seventh switch (315);

one end of the seventh switch (315) is connected to the output terminal of the first inverter (314), and another end of the seventh switch (315) is connected to the sixth junction (316);

one end of the ninth switch (318) is connected to a power supply VDD, and another end of the ninth switch (318) is connected to the sixth junction (316);

one end of the eighth switch (317) is connected to the sixth junction (316), and another end is connected to the eighth junction (325) respectively;

a gate terminal of the third NMOS transistor (319) is connected to the sixth junction (316), and a source terminal and a drain terminal of the third NMOS transistor (319) are grounded respectively;

one end of the tenth switch (320) is connected to the seventh junction (321), and another end of the tenth switch (320) is connected to an output terminal of the first inverter (314);

one end of the twelfth switch (323) is connected to the power supply VDD, and another end of the twelfth switch (323) is connected to the seventh junction (321);

one end of the eleventh switch (322) is connected to the seventh junction (321), and another end of the eleventh switch (322) is connected to the eighth junction (322);

a gate terminal of the fourth NMOS transistor (324) is connected to the seventh junction (321), and a source terminal and a drain terminal of the fourth NMOS transistor (324) are grounded respectively;

an input terminal of the second inverter (326) is connected to the eighth junction (325), and an output terminal is connected to the thirteenth switch (327);

one end of the thirteenth switch (327) is connected to an output terminal of the second inverter (326), and another end of the thirteenth switch (327) is connected to the ninth junction (328);

one end of the fifteenth switch (330) is connected to the power supply VDD, and another end of the fifteenth switch (330) is connected to the ninth junction (328);

one end of the fourteenth switch (329) is connected to the ninth junction (328), and another end of the fourteenth switch (329) is connected to the eleventh junction (337);

a gate terminal of the third NMOS transistor (331) is connected to the ninth junction (328), and the source and drain terminals of the third NMOS transistor (331) are grounded;

one end of the sixteenth switch (332) is connected to an output terminal of the second inverter (326), and another end of the sixteenth switch (332) is connected to the tenth junction (333);

one end of the eighteenth switch (335) is connected to the power supply VDD, and another end of the eighteenth switch (335) is connected to the tenth junction (333);

one end of the seventeenth switch (334) is connected to the tenth junction (333), and another end of the seventeenth switch (334) is connected to the eleventh junction (337);

a gate terminal of the sixth NMOS transistor (336) is connected to the tenth junction (333), and a source terminal and a drain terminal of the sixth NMOS transistor (336) are grounded respectively; and

an input terminal of the third inverter (338) is connected to the eleventh junction (337), and an output terminal of the third inverter (338) is connected to the sixth output terminal (339).

6. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein the output selection module (400) includes:

a fourth input terminal (401), a fifth input terminal (402), a sixth input terminal (403), a fifth inverter (404), a sixth inverter (405), an eleventh AND gate (406), a twelfth AND gate (407), a thirteenth AND gate (408), a fourteenth AND gate (409), a seventh output terminal (410), and an eighth output terminal (411),

wherein the fourth input terminal (401) is connected to the sixth output terminal (339);

the fifth input terminal (402) is connected to the first input terminal (201);

the sixth input terminal (403) is connected to the second input terminal (202);

the seventh output terminal (410) is connected to the counter A for accessing the Q1 signal;

the eighth output terminal (411) is connected to the counter B for accessing the Q0 signal;

an input terminal of the fifth inverter (404) is connected to the fifth input terminal (402), and an input terminal of the sixth inverter (405) is connected to the sixth input terminal (403);

one input terminal of the eleventh AND gate (406) is connected to the sixth input terminal (403), and another end of the eleventh AND gate (406) is connected to an output terminal of the fifth inverter (404);

one input terminal of the twelfth AND gate (407) is connected to the output terminal of the fifth inverter (404), and another input terminal of the twelfth AND gate (407) is connected to an output terminal of the sixth inverter (405);

one input terminal of the thirteenth AND gate (408) is connected to the output terminal of the eleventh AND gate (406), another end of the thirteenth AND gate (408) is connected to the fourth input terminal (401), and an output terminal of the thirteenth AND gate (408) is connected to the seventh output terminal (410); and

one input terminal of the fourteenth AND gate (409) is connected to the fourth input terminal (401), and another input terminal of the fourteenth AND gate (409) is connected to an output terminal of the twelfth AND gate (407), and an output terminal of fourteenth AND gate (409) is connected to the eighth output terminal (411).

7. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein the timing logic module (100) is in a state switched among S0, S1, S2 and S3 states under control of the level voltage input into the X and Y input terminals;

when the timing logic module (100) is in the S2 state, a combination of the Q1 and Q0 signals is “

10”

,

the first input terminal (201) is at a high level voltage of “

1”

, the second input terminal (202) is at a low level voltage of “

0”

,

the first output terminal (220) is at the high level voltage of “

1”

to control the third switch (306), the ninth switch (318) and the fifteenth switch (330) to be switched on,

the second output terminal (221) is at the low level voltage of “

0”

to control the first switch (303), the second switch (305), the seventh switch (315), the eighth switch (317), the thirteenth switch (327) and the fourteenth switch (329) to be switched off,

the third output terminal (222) is at the low level voltage of “

0”

to control the fourth switch (308), the fifth switch (310), the tenth switch (320), the eleventh switch (322), the sixteenth switch (332) and the seventeenth switch (334) to be switched off,

the fourth output terminal (223) is at the low level voltage of “

0”

to control the sixth switch (311), the twelfth switch (323) and the eighteenth switch (335) to be switched off,

the fifth output terminal (224) is at the high level voltage of “

1” and

is connected to the third input terminal (301), and gate terminals of the first NMOS transistor (307), the third NMOS transistor (319) and the fifth NMOS transistor (331) are in a VDD voltage stress state.

8. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein when the timing logic module (100) is in the S0 state, a combination of the Q1 and Q0 signals is “

00”

,

the first input terminal (201) is at a low level voltage of “

0”

, the second input terminal (202) is at the low level voltage of “

0”

,

the first output terminal (220) is at the low level voltage of “

0”

to control the third switch (306), the ninth switch (318) and the fifteenth switch (330) to be switched off,

the second output terminal (221) is at a high level voltage of “

1”

to control the first switch (303), the second switch (305), the seventh switch (315), the eighth switch (317), the thirteenth switch (327) and the fourteenth switch (329) to be switched on,

the third output terminal (222) is at the low level voltage of “

0”

to control the fourth switch (308), the fifth switch (310), the tenth switch (320), the eleventh switch (322), the sixteenth switch (332) and the seventeenth switch (334) to be switched off,

the fourth output terminal (223) is at the low level voltage of “

0”

to control the sixth switch (311), the twelfth switch (323) and the eighteenth switch (335) to be switched off,

the fifth output terminal (224) is at the high level voltage of “

1” and

is connected to the third input terminal (301), the digital conversion module for TDDB performance degradation (300) is a circuit in an oscillation state, including the first NMOS transistor (307), the third NMOS transistor (319) and the fifth NMOS transistor (331), and the sixth output terminal (339) outputs a periodic signal with alternate high and low level voltage, with an oscillation frequency as the second frequency value.

9. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein when the timing logic module (100) is in the S1 state, a combination of the Q1 and Q0 signals is “

01”

,

the first input terminal (201) is at a low level voltage of “

0”

, the second input terminal (202) is at a high level voltage of “

1”

,

the first output terminal (220) is at the low level voltage of “

0”

to control the third switch (306), the ninth switch (318) and the fifteenth switch (330) to be switched off,

the second output terminal (221) is at the low level voltage of “

0”

to control the first switch (303), the second switch (305), the seventh switch (315), the eighth switch (317), the thirteenth switch (327) and the fourteenth switch (329) to be switched off,

the third output terminal (222) is at the high level voltage of “

1”

to control the fourth switch (308), the fifth switch (310), the tenth switch (320), the eleventh switch (322), the sixteenth switch (332) and the seventeenth switch (334) to be switched on,

the fourth output terminal (223) is at the low level voltage of “

0”

to control the sixth switch (311), the twelfth switch (323) and the eighteenth switch (335) to be switched off,

the fifth output terminal (224) is at the high level voltage of “

1” and

is connected to the third input terminal (301), the digital conversion module for TDDB performance degradation (300) is a circuit in a oscillation state, including the second NMOS transistor (312), the 4rd NMOS transistor (324) and the sixth NMOS transistor (336), and the sixth output terminal (339) outputs a periodic signal with alternate high and low level voltage, with an oscillation frequency as the first frequency value.

10. The on-chip TDDB degradation monitoring and failure early warning circuit for SoC of claim 1, wherein property of TDDB performance degradation is obtained by comparing the second frequency value in counter A with the first frequency value in counter B.