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Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

  • US 10,504,585 B2
  • Filed: 11/22/2017
  • Issued: 12/10/2019
  • Est. Priority Date: 04/10/2013
  • Status: Active Grant
First Claim
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1. A method of selecting a preferred floating body SRAM cell type by a memory compiler for use in array design, wherein the preferred floating body SRAM cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell, said method comprising:

  • a user inputting preferred design criteria to at least one processor of the memory compiler;

    the memory compiler evaluating the preferred design criteria by executing at least one algorithm configured to select the preferred floating body SRAM cell type based on the design criteria inputs received;

    determining whether the preferred floating body SRAM cell type can be identified based upon the preferred design criteria inputted and the at least one algorithm executed; and

    selecting the preferred floating body SRAM cell type when identifiable;

    providing the user with an array design requested by the user, wherein the array design employs floating body SRAM cells of the preferred floating body SRAM cell type; and

    when a preferred floating body SRAM cell type cannot be clearly identified, providing the user with a report identifying floating body SRAM cell types that were eliminated based on the preferred design criteria, providing remaining SRAM cell type choices that were not eliminated and indicating which are preferable for selection; and

    requesting the user to adjust the preferred design criteria or provide an override so as to manually select the preferred floating body SRAM cell type.

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