Scalable floating body memory cell for memory compilers and method of using floating body memories with memory compilers

• US 10,504,585 B2
• Filed: 11/22/2017
• Issued: 12/10/2019
• Est. Priority Date: 04/10/2013
• Status: Active Grant

• Current Assignee: Zeno Semiconductor, Inc.
• Original Assignee: Zeno Semiconductor, Inc.
• Inventors: Louie, Benjamin S., Widjaja, Yuniarto, Or-Bach, Zvi
• Primary Examiner(s): Nguyen, Nha T
• Application Number:
  US15/820,869
• Publication Number:
  US 20180096721A1
• Time in Patent Office: 748 Days
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/337 Design optimisation
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/417 for memory cells of the field-effect type
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Claims

1. A method of selecting a preferred floating body SRAM cell type by a memory compiler for use in array design, wherein the preferred floating body SRAM cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell, said method comprising:

a user inputting preferred design criteria to at least one processor of the memory compiler;

the memory compiler evaluating the preferred design criteria by executing at least one algorithm configured to select the preferred floating body SRAM cell type based on the design criteria inputs received;

determining whether the preferred floating body SRAM cell type can be identified based upon the preferred design criteria inputted and the at least one algorithm executed; and

selecting the preferred floating body SRAM cell type when identifiable;

providing the user with an array design requested by the user, wherein the array design employs floating body SRAM cells of the preferred floating body SRAM cell type; and

when a preferred floating body SRAM cell type cannot be clearly identified, providing the user with a report identifying floating body SRAM cell types that were eliminated based on the preferred design criteria, providing remaining SRAM cell type choices that were not eliminated and indicating which are preferable for selection; and

requesting the user to adjust the preferred design criteria or provide an override so as to manually select the preferred floating body SRAM cell type.

2. The method of claim 1, wherein floating body SRAM cell types from which the preferred floating body SRAM cell type is selected include:

one-transistor floating body SRAM cell, two-transistor floating body SRAM cell, three-transistor floating body SRAM cell, four-transistor floating body SRAM cell, dual-port floating body SRAM cell and pseudo dual port floating body SRAM cell.

3. The method of claim 1, wherein the array design is an array design selected from the group consisting of:

memory array circuit design, memory array layout, memory array timing model, memory array functional model, memory array timing specifications, and memory array symbol.

4. The method of claim 1, wherein said preferred design criteria include at least one of:

speed/performance, density, standby power, port access, memory size, reliability, byte size, page size or erase block size.

5. The method of claim 1, wherein the preferred design criteria consists of a single design criterion.

6. The method of claim 1, wherein the preferred design criteria comprise a combination of a plurality of said preferred design criteria.

7. The method of claim 1, further comprising ranking said design criteria to prioritize importance of said design criteria.

8. The method of claim 1, wherein when the preferred floating body SRAM cell type cannot be clearly identified, said method further comprises:

adjusting the design criteria or providing an override;

when adjusted design criteria are provided, the memory compiler evaluating the adjusted design criteria by executing the at least one algorithm configured to select the preferred floating body SRAM cell type based on the adjusted design criteria inputs received;

determining whether the preferred floating body SRAM cell type can be identified based upon the adjusted design criteria inputted and the at least one algorithm executed;

selecting the preferred floating body SRAM cell type when identifiable; and

providing the user with an array design requested by the user, wherein the array design employs floating body SRAM cells of the preferred floating body SRAM cell type;

when the preferred floating body SRAM cell type cannot be clearly identified based on the adjusted design criteria, providing the user with a report identifying floating body SRAM cell types that were eliminated based on the adjusted design criteria, providing remaining SRAM cell type choices that were not eliminated and indicating which are preferable for selection; and

requesting the user to further adjust the preferred design criteria or provide an override so as to manually select the preferred floating body SRAM cell type; and

when an override is provided, providing the user with an array design requested by the user, wherein the array design employs floating body SRAM cells of the preferred floating body SRAM cell type selected by the override.

9. A method of selecting a floating body SRAM cell type by a memory compiler for use in a memory design, wherein the floating body SRAM cell comprises a floating body region configured to be charged to a level indicative of a state of the memory cell, said method comprising:

a user inputting at least one design criterion to at least one processor of the memory compiler;

the memory compiler evaluating the at least one design criterion by executing at least one algorithm configured to select the preferred floating body SRAM cell type from a plurality of different floating body SRAM cell types based on the at least one design criterion input received;

the memory compiler determining whether the preferred floating body SRAM cell type can be identified from the plurality of different floating body SRAM cell types based upon the at least one design criterion inputted and the at least one algorithm executed; and

selecting the preferred floating body SRAM cell type when identifiable;

providing the user with a memory design requested by the user, wherein the memory design employs floating body SRAM cells of the preferred floating body SRAM cell type; and

when the preferred floating body SRAM cell type cannot be clearly identified, eliminating at least one of the different floating body SRAM cell types as a candidate for selection and providing the user with a report identifying the at least one floating body SRAM cell type or types that was or were eliminated based on the evaluation using the at least one design criterion, and requesting the user to adjust the at least one design criterion input or provide an override so as to manually select the preferred floating body SRAM cell type as an override-selected preferred floating body SRAM cell type.

10. The method of claim 9, wherein when the preferred floating body SRAM cell type cannot be clearly identified, said method further comprising providing the user with a basis for elimination of each of the at least one floating body SRAM cell type or types that was or were eliminated, wherein said basis identifies at least one of the at least one design criterion upon which each floating body SRAM cell type was eliminated.

11. The method of claim 9, wherein when the preferred floating body SRAM cell type cannot be clearly identified, said method further comprising identifying to the user remaining floating body SRAM cell type choices from floating body SRAM cell types of said plurality of floating body SRAM types that were not eliminated.

12. The method of claim 11, wherein upon said identifying remaining floating body SRAM cell type choices from floating body SRAM cell types of said plurality of floating body SRAM types that were not eliminated, said method further comprising identifying which of said remaining floating body SRAM cell types are best options based upon the at least one inputted design criterion.

13. The method of claim 12, further comprising providing to the user basis for the best options by identifying each of the at least one inputted design criterion that applies to each of the floating body SRAM cell types considered to be the best options.

14. The method of claim 9, wherein the memory design is a memory design selected from one memory design from the group consisting of:

memory array circuit design, memory array layout, memory array timing model, memory array functional model, timing specifications, and memory array symbol.

15. The method of claim 9, wherein said floating body SRAM cell types from which the preferred floating body SRAM cell type is selected include:

one-transistor floating body SRAM cell, two-transistor floating body SRAM cell, three-transistor floating body SRAM cell, four-transistor floating body SRAM cell, dual-port floating body SRAM cell and pseudo dual port floating body SRAM cell.

16. The method of claim 9, further comprising:

in response to said requesting the user to adjust the at least one design criterion input or provide an override so as to manually select an override-selected preferred floating body SRAM cell type, adjusting the at least one design criterion;

the memory compiler evaluating the adjusted at least one design criterion by executing the at least one algorithm configured to select the preferred floating body SRAM cell type from the remaining floating body SRAM cell type choices from floating body SRAM cell types of said plurality of floating body SRAM types that were not eliminated, based on the adjusted at least one design criterion input received;

the memory compiler determining whether a preferred floating body SRAM cell type can be identified from the remaining floating body SRAM cell types based upon the adjusted at least one design criterion inputted and the at least one algorithm executed; and

selecting the preferred floating body SRAM cell type when identifiable, and outputting a report to the user, said report providing details upon which the preferred floating body SRAM cell type was selected;

providing the user with a memory design requested by the user, wherein the memory design employs floating body SRAM cells of the preferred floating body SRAM cell type; and

when the preferred floating body SRAM cell type cannot be clearly identified, eliminating at least one of the different floating body SRAM cell types as a candidate for selection and providing the user with a report identifying the at least one of the different floating body SRAM cell type or types that was or were eliminated based on the evaluation using the at least one design criterion, and requesting the user to adjust the at least one design criterion input or provide an override so as to manually select the preferred floating body SRAM cell type as an override-selected preferred floating body SRAM cell type.

17. The method of claim 9, further comprising:

in response to said requesting the user to adjust the at least one design criterion input or provide an override so as to manually select the override-selected preferred floating body SRAM cell type;

adjusting the at least one design criterion, providing an override so as to manually select the override-selected preferred floating body SRAM cell type;

the memory compiler providing the user with a memory design requested by the user, wherein the memory design employs floating body SRAM cells of the override-selected preferred floating body SRAM cell type.

18. The method of claim 9, wherein the design criteria available to the user for said inputting at least design criterion are ranked to prioritize the relative importance of each said design criterion.

19. The method of claim 9, wherein said executing at least one algorithm includes executing an algorithm configured to select the preferred floating body SRAM cell type by process of elimination, selecting the floating body SRAM cell type that has the greatest number of criteria inputted by the user.

20. The method of claim 9, wherein said executing at least one algorithm includes executing an algorithm configured to select the preferred floating body SRAM cell type by average weighting of ranked features for each floating body SRAM cell type and then selecting the floating body SRAM cell type with the highest weighted average.