Memory device architecture

• US 10,504,589 B2
• Filed: 09/13/2018
• Issued: 12/10/2019
• Est. Priority Date: 10/12/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Castro, Hernan A., Flores, Everardo Torres, Hirst, Jeremy M.
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US16/130,682
• Publication Number:
  US 20190013069A1
• Time in Patent Office: 453 Days
• Field of Search: 365 46, 365 94, 365100, 365113, 365129, 365148, 365158, 365163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: H10B 63/24 of the Ovonic threshold switching type
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

Row electrode drivers and column electrode drivers for a memory device are distributed within a footprint share by a memory cell array.

Claims

1. A device, comprising:

a plurality of memory cells within a footprint of the device; and

a plurality of word line drivers and digit line drivers in a circuit level positioned below the plurality of memory cells, wherein the circuit level comprises a plurality of word line driver connection points and digit line driver connection points within the footprint.

2. The device of claim 1, wherein the plurality of word line drivers are distributed across and within the footprint in a plurality of word line driver regions, and wherein the plurality of digit line drivers are distributed across and within the footprint in a plurality of digit line driver regions.

3. The device of claim 2, wherein word line electrodes connecting the plurality of word line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the word line electrodes relative to one another along their axis of elongation.

4. The device of claim 3, wherein digit line electrodes connecting the plurality of digit line drivers to the plurality of memory cells of the device are staggered relative to one another by shifting the digit line electrodes relative to one another along their axis of elongation.

5. The device of claim 1, wherein the plurality of memory cells comprises word lines positioned along a first direction and digit lines positioned along a second direction different from the first direction.

6. The device of claim 1, further comprising:

a plurality of word lines each coupled with at least one of the plurality of word line drivers at a different vertical level from the plurality of word line drivers.

7. The device of claim 6, wherein each word line driver connection point of the plurality of word line driver connection points is positioned along a word line direction within a word line driver region of a plurality of word line driver regions.

8. The device of claim 1, further comprising:

a plurality of digit lines each coupled with at least one of the plurality of digit line drivers at a different vertical level from the plurality of digit line drivers.

9. The device of claim 8, wherein each of the digit line driver connection points is positioned along a digit line direction within a digit line driver region of a plurality of digit line driver regions.