System-in-package module with memory

• US 10,504,603 B2
• Filed: 07/24/2017
• Issued: 12/10/2019
• Est. Priority Date: 10/23/2013
• Status: Active Grant

• Current Assignee: Etron Technology Inc
• Original Assignee: Etron Technology Inc
• Inventors: Ken, Weng-Dah, Lu, Chao-Chun
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): Gandhi, Dipakkumar B
• Application Number:
  US15/657,235
• Publication Number:
  US 20170323687A1
• Time in Patent Office: 869 Days
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17181 On opposite sides of the body
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 Bump and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 2225/06589 : Thermal management, e.g. cooling
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15151 : the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A system-in-package module with memory includes a non-memory chip, a substrate, and a memory chip. The non-memory chip has a first portion and a second portion. The substrate has a window and the substrate is electrically connected to the second portion of the non-memory chip. The memory chip is placed into the window of the substrate to electrically connect the first portion of the non-memory chip, and there is no direct metal connection between the memory chip and the substrate.

Claims

1. A system-in-package (SIP) module with memory, the SIP module comprising:

a cache memory;

a memory controller;

a memory; and

a substrate, wherein the cache memory, the memory controller, and the memory are co-packaged over the substrate, and the cache memory and the memory controller are formed on a same semiconductor chip;

wherein the memory controller accesses the memory and the cache memory through a first reconfigurable bus, transmits data to an external circuit or receives data from the external circuit through a second reconfigurable bus, and the memory controller is capable of dynamically changing a first swing voltage and an address width of the first reconfigurable bus according to a stacked number corresponding to the memory and a bus width of the first reconfigurable bus, or a second swing voltage and an address width of the second reconfigurable bus according to the stacked number corresponding to the memory and a bus width of the second reconfigurable bus, or the first swing voltage and the address width of the first reconfigurable bus and the second swing voltage and the address width of the second reconfigurable bus according to the stacked number corresponding to the memory, the bus width of the first reconfigurable bus, and the bus width of the second reconfigurable bus.

2. The SIP module of claim 1, wherein the cache memory, the memory controller, and the memory are installed on the substrate respectively, or are installed on the substrate after the cache memory, the memory controller, and the memory are stacked together.

3. The SIP module of claim 2, wherein the same semiconductor chip is a Si Chip made according to a complementary metal-oxide-semiconductor (CMOS) process.

4. The SIP module of claim 1, wherein the cache memory is a static random access memory (SRAM) or a dynamic random access memory (DRAM), and the memory is a DRAM, or a plurality of DRAMs stacked together, and an operation speed or a band width of the cache memory is greater than an operation speed or a band width of the memory.

5. The SIP module of claim 1, wherein the memory controller is used for accessing data of the cache memory or the memory according to commands of the SIP module, correcting data errors stored in the cache memory or the memory, dynamically changing the bus width of the first reconfigurable bus, or dynamically changing the bus width, or a second operation frequency of the second reconfigurable bus.

6. The SIP module of claim 1, wherein the memory is installed above the cache memory and is electrically connected to the cache memory through silicon vias (TSV).

7. A system-in-package module with memory, the SIP module comprising:

a non-memory chip having a first portion and a second portion, wherein the non-memory chip comprises a plurality of first electrical contacts and a plurality of second electrical contacts, and the plurality of first electrical contacts and the plurality of second electrical contacts are installed on the first portion and the second portion of the non-memory chip, respectively;

a memory having a plurality of third electrical contacts installed on one side thereof;

a substrate having a plurality of fourth electrical contacts installed on one side thereof and a plurality of fifth electrical contacts installed on another side thereof; and

an additional memory covering the non-memory chip, the memory, and the substrate, wherein the additional memory, the memory, and the non-memory chip form a three-layer structure, the non-memory chip exists between the additional memory and the memory, and the additional memory is directly electrically connected to the substrate;

wherein the plurality of first electrical contacts are electrically connected to the plurality of third electrical contacts to make the memory be electrically connected to the non-memory chip, the plurality of second electrical contacts are electrically connected to the plurality of fourth electrical contacts to make the substrate be electrically connected to the non-memory chip, and the substrate and the memory are both electrically connected to the same side of the non-memory chip or electrically connected to different sides of the non-memory chip;

wherein there is no direct electrical connection between the memory and the substrate.

8. The SIP module of claim 7, wherein materials of the plurality of first electrical contacts, the plurality of second electrical contacts, the plurality of third electrical contacts, the plurality of fourth electrical contacts, or the plurality of fifth electrical contacts comprise solder or copper.