Method of adjusting signal to noise ratio of SRAM and invertor structure
First Claim
1. A method of adjusting a signal-to-noise ratio (SNR) of a static random access memory (SRAM), comprising:
- providing a substrate, a first long fin structure and a second long fin structure disposed on the substrate, a first short fin structure and a second short fin structure disposed on the substrate and between the first long fin structure and the second long fin structure, a first gate line crossing the first long fin structure, the first short fin structure, and the second long fin structure, and a second gate line crossing the first long fin structure, the second short fin structure and the second long fin structure, wherein the first long fin structure comprises a first side and a second side, the second side faces the first short fin structure, the first side is opposite to the second side, the second long fin structure comprises a third side and a fourth side, the fourth side faces the second short fin structure, and the third side is opposite to the fourth side; and
performing a gate line cutting step, comprising;
removing the second gate line between the first long fin structure and the second short fin structure by a first length;
removing the first gate line between the second long fin structure and the first short fin structure by the first length;
removing the first gate line at the first side of the first long fin structure by a second length; and
removing the second gate line at the third side of the second long fin structure by the second length;
wherein an SNR of an SRAM having the first length greater than the second length is greater than an SNR of an SRAM having the first length equal to the second length.
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Abstract
An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.
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Citations
9 Claims
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1. A method of adjusting a signal-to-noise ratio (SNR) of a static random access memory (SRAM), comprising:
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providing a substrate, a first long fin structure and a second long fin structure disposed on the substrate, a first short fin structure and a second short fin structure disposed on the substrate and between the first long fin structure and the second long fin structure, a first gate line crossing the first long fin structure, the first short fin structure, and the second long fin structure, and a second gate line crossing the first long fin structure, the second short fin structure and the second long fin structure, wherein the first long fin structure comprises a first side and a second side, the second side faces the first short fin structure, the first side is opposite to the second side, the second long fin structure comprises a third side and a fourth side, the fourth side faces the second short fin structure, and the third side is opposite to the fourth side; and performing a gate line cutting step, comprising; removing the second gate line between the first long fin structure and the second short fin structure by a first length; removing the first gate line between the second long fin structure and the first short fin structure by the first length; removing the first gate line at the first side of the first long fin structure by a second length; and removing the second gate line at the third side of the second long fin structure by the second length; wherein an SNR of an SRAM having the first length greater than the second length is greater than an SNR of an SRAM having the first length equal to the second length. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification