Fin field effect transistor (FinFET) device with protection layer

• US 10,504,893 B2
• Filed: 08/29/2014
• Issued: 12/10/2019
• Est. Priority Date: 08/29/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Shiang-Bau
• Primary Examiner(s): Gebremariam, Samuel A
• Assistant Examiner(s): Beardsley, Jonas T
• Application Number:
  US14/472,566
• Publication Number:
  US 20160064377A1
• Time in Patent Office: 1,929 Days
• Field of Search: None
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a first fin structure extending above a substrate and an isolation structure formed on the substrate. The first fin structure is embedded in the isolation structure, and the first fin structure has an upper portion and a lower portion. The upper portion is above the isolation structure, and the lower portion is below the isolation structure. The FinFET device structure also includes a protection layer formed on the sidewalls of the lower portion of the first fin structure.

Claims

1. A fin field effect transistor (FinFET) device structure, comprising:

a first silicon fin structure having a first sidewall and a second sidewall extending above a substrate, wherein the first sidewall and the second sidewall are at opposite sides of a center plane of the first silicon fin structure, and the first sidewall and the second sidewall are asymmetric at the same level to the center plane of the first silicon fin structure;

a second silicon fin structure adjacent to the first silicon fin structure, wherein the second silicon fin structure has a third sidewall facing towards the second sidewall of the first silicon fin structure;

an isolation structure formed on the substrate, wherein a lower portion of the first silicon fin structure is embedded in the isolation structure and an upper portion of the first silicon fin structure extends from the isolation structure; and

a nitride layer directly formed on the lower portion of the first silicon fin structure, wherein the nitride layer is a single layer, and the nitride layer does not extend above the isolation structure,

wherein the first sidewall has a first inclination with respect to a top surface of the isolation structure, a top portion of the second sidewall has a second inclination with respect to the top surface of the isolation structure, and a bottom portion of the second sidewall has a third inclination with respect to the top surface of the isolation structure, and the first inclination, the second inclination, and the third inclination are all different, and wherein a bottom portion of the third sidewall intersects the bottom portion of the second sidewall to form a V-shaped structure.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1,

wherein the nitride layer is extended from the second sidewall of the first silicon fin structure to the third sidewall of the second silicon fin structure.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the bottom portion of the second sidewall of the first silicon fin structure is entirely covered by the isolation structure while the top portion of the second sidewall of the first silicon fin structure is partially covered by the isolation structure.

4. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein a top portion of the third sidewall has a fourth inclination with respect to the top surface of the isolation structure, and the bottom portion of the third sidewall has a fifth inclination with respect to the top surface of the isolation structure, and the fourth inclination is different from the fifth inclination.

5. The fin field effect transistor (FinFET) device structure as claimed in claim 4, wherein the nitride layer is in direct contact with the top portion of the third sidewall, the bottom portion of the third sidewall, the top portion of the second sidewall, and the bottom portion of the second sidewall.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the nitride layer and the top surface of the isolation structure form a pentagonal-shaped structure.

19. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the isolation structure has inwardly inclined sidewalls that form a tapered portion of the isolation structure.

7. A fin field effect transistor (FinFET) device structure, comprising:

a substrate;

a first fin structure formed on the substrate, wherein the fin structure has a first sidewall and a second sidewall;

a second fin structure formed adjacent to the first fin structure, wherein the second fin structure has a third sidewall and a fourth sidewall, and wherein the third sidewall intersects the second sidewall to form a first V-shaped structure; and

an isolation structure formed on the substrate and between the first fin structure and the second fin structure, wherein the first sidewall of the first fin structure has a first inclination with respect to a top surface of the isolation structure, a top portion of the second sidewall of the first fin structure has a second inclination with respect to the top surface of the isolation structure, and a bottom portion of the second sidewall of the first fin structure has a third inclination with respect to the top surface of the isolation structure, and the first inclination, the second inclination, and the third inclination are all different;

a nitride layer having a first portion directly formed on the bottom portion of the second sidewall of the first fin structure and a second portion directly formed on a bottom portion of the third sidewall of the second fin structure, wherein the nitride layer is extended from the second sidewall to the third sidewall, the first portion of the nitride layer and the second portion of the nitride layer form a second V-shaped structure, wherein the nitride layer is a single layer and comprises silicon nitride, silicon oxynitride, or silicon oxycarbonnitride, and the isolation structure has inwardly inclined sidewalls that form a tapered portion of the isolation structure.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the first fin structure has an upper portion and a lower portion.

9. The fin field effect transistor (FinFET) device structure as claimed in claim 8, wherein a height ratio of the upper portion of the first fin structure to the lower portion of the first fin structure is in a range from 0.1 to about 0.5.

10. The fin field effect transistor (FinFET) device structure as claimed in claim 7,

wherein the bottom portion of the second sidewall of the first silicon fin structure is entirely covered by the isolation structure and the top portion of the second sidewall of the first silicon fin structure is partially covered by the isolation structure.

11. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the nitride layer does not extend above the isolation structure.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 11, wherein the nitride layer is along the lines of the inwardly inclined sidewalls of the isolation structure.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the nitride layer is along the lines of the inwardly inclined sidewalls of the isolation structure.

14. The fin field effect transistor (FinFET) device structure as claimed in claim 7, wherein the second sidewall of the first fin structure and the third sidewall of the second fin structure adjoin together so that the second sidewall of the first fin structure, the third sidewall of the second fin structure and the top surface of the isolation structure form a pentagonal-shaped structure.

20. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the nitride layer is along the lines of the inwardly inclined sidewalls of the isolation structure.

15. A fin field effect transistor (FinFET) device structure, comprising:

a first silicon fin structure having a first sidewall and a second sidewall extending above a substrate;

a second silicon fin structure having a third sidewall and a fourth sidewall formed over the substrate;

an isolation structure formed on the substrate, wherein the first silicon fin structure is embedded in the isolation structure, the first silicon fin structure has an upper portion and a lower portion, the upper portion is above the isolation structure, and the lower portion is below the isolation structure; and

a first portion of a nitride layer directly formed on the second sidewall of the first silicon fin structure and a second portion of the nitride layer directly formed on the third sidewall of the second silicon fin structure, wherein the first portion of the nitride layer, the second portion of the nitride layer and a top surface of the isolation structure form a pentagonal-shaped structure,

wherein the nitride layer is a single layer and comprises silicon nitride, silicon oxynitride, or silicon oxycarbonnitride, and the nitride layer does not extend above the isolation structure, and

wherein the first sidewall of the first silicon fin structure has a first inclination with respect to a top surface of the isolation structure, a top portion of the second sidewall of the first silicon fin structure has a second inclination with respect to the top surface of the isolation structure, and a bottom portion of the second sidewall of the first silicon fin structure has a third inclination with respect to the top surface of the isolation structure, and the first inclination, the second inclination, and the third inclination are all different.

16. The fin field effect transistor (FinFET) device structure as claimed in claim 15, wherein the nitride layer has a thickness selectable from any of a plurality of thicknesses in a range from 0.5 nm to about 10 nm.

17. The fin field effect transistor (FinFET) device structure as claimed in claim 15, wherein a height ratio of the upper portion of the first silicon fin structure to the lower portion of the first silicon fin structure is in a range from 0.1 to about 0.5.

18. The fin field effect transistor (FinFET) device structure as claimed in claim 15, wherein the first silicon fin structure has a width that gradually increases from the upper portion to the lower portion.