HVMOS reliability evaluation using bulk resistances as indices

• US 10,504,896 B2
• Filed: 06/01/2018
• Issued: 12/10/2019
• Est. Priority Date: 05/19/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Chi-Feng, Chen, Chia-Chung, Lu, Tse-Hua
• Primary Examiner(s): Purvis, Sue A
• Assistant Examiner(s): Klein, Jordan M
• Application Number:
  US15/995,778
• Publication Number:
  US 20180277539A1
• Time in Patent Office: 557 Days
• Field of Search: None
• CPC Class Codes: G01R 27/08 Measuring resistance by measuring both voltage and current
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of determining the reliability of a high-voltage PMOS (HVPMOS) device includes determining a bulk resistance of the HVPMOS device, and evaluating the reliability of the HVPMOS device based on the bulk resistance.

Claims

1. A structure comprising:

a semiconductor substrate;

a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed at a surface of the semiconductor substrate, wherein the plurality of HVPMOS devices form an array comprising a plurality of rows and a plurality of columns; and

an n-type guard ring comprising a plurality of portions, each encircling one of the plurality of HVPMOS devices, with neighboring ones of the plurality of HVPMOS devices separated from each other by the n-type guard ring.

2. The structure of claim 1 further comprising a plurality of isolation regions separated from each other by the n-type guard ring, and each of the plurality of HVPMOS devices comprises an active region encircled by one of the plurality of isolation regions.

3. The structure of claim 2, wherein the plurality of isolation regions comprise an isolation region encircled by one of the plurality of portions, with no High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) having any active region that is also encircled by the isolation region.

4. The structure of claim 3, wherein each of the plurality of portions encircles an active region of a single HVPMOS device, and no active region of any additional MOS device is encircled by any of the plurality of isolation regions.

5. The structure of claim 2, wherein the active region of the each of the plurality of HVPMOS devices has an active-region-to-guard-ring spacing smaller than about 2 μ

m, and the active-region-to-guard-ring spacing is between the active region and a nearest portion of the n-type guard ring.

6. The structure of claim 1, wherein a region encircled by the n-type guard ring has a length and a width smaller than the length, with the width being smaller than about 30 μ

m.

7. The structure of claim 6, wherein the width is measured in a direction perpendicular to lengthwise directions of active regions of the plurality of HVPMOS devices.

8. The structure of claim 1 further comprising a High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device encircled by an additional guard ring, wherein the HVNMOS device has an additional active-region-to-guard-ring spacing greater than 2 μ

m.

9. The structure of claim 8, wherein the HVNMOS device comprises an active region encircled by an additional isolation region, and no addition MOS device has any active region encircled by the additional isolation region.

10. The structure of claim 1, wherein the n-type guard-ring comprises a portion of the semiconductor substrate that are heavily doped as n-type.

11. A structure comprising:

a semiconductor substrate;

a heavily doped semiconductor region extending into the semiconductor substrate wherein the heavily doped semiconductor region forms a guard ring;

a plurality of isolation regions extending into the semiconductor substrate and forming an array, wherein each of the plurality of isolation regions is separated from other ones of the plurality of isolation regions by the heavily doped semiconductor region;

a plurality of active regions, each encircled by one of the plurality of isolation regions, wherein the plurality of active regions have active-region-to-guard-ring spacings smaller than about 2 pm; and

a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices formed based on the plurality of active regions.

12. The structure of claim 11, wherein each of the plurality of isolation regions encircles a single active region.

13. The structure of claim 11, wherein the heavily doped semiconductor region forms a plurality of rings that are interconnected with each other, and inside each of the plurality of rings, a single one of the plurality of HVPMOS devices is formed.

14. The structure of claim 11, wherein each of the plurality of isolation regions has a length and a width smaller than the length, with the width being smaller than about 30 μ

m.

15. The structure of claim 11 further comprising a High-Voltage N-type Metal-Oxide-Semiconductor (HVNMOS) device encircled by an additional heavily doped semiconductor region, wherein the HVNMOS device has an additional active-region-to-guard-ring spacing greater than 2 μ

m.

16. The structure of claim 11, wherein the heavily doped semiconductor region has an n-type impurity concentration higher than about 1×

10¹⁹/cm³.

17. A structure comprising:

a semiconductor substrate;

a heavily doped semiconductor region extending into the semiconductor substrate, wherein the heavily doped semiconductor region is of n-type;

a plurality of Shallow Trench Isolation (STI) regions extending into the semiconductor substrate and forming an array, wherein each of the plurality of STI regions is separated from other ones of the plurality of STI regions by the heavily doped semiconductor region;

a plurality of active regions, each encircled by one of the plurality of STI regions, wherein each of the plurality of STI regions has a rectangular top-view shape, and has a length and a width smaller than the length, with the width being smaller than about 30 μ

m; and

a plurality of High-Voltage P-type Metal-Oxide-Semiconductor (HVPMOS) devices, each being formed based on one of the plurality of active regions.

18. The structure of claim 17, wherein each of the plurality of STI regions encircles a single active region.

19. The structure of claim 17, wherein the heavily doped semiconductor region forms a plurality of rings that are interconnected with each other to form a continuous semiconductor region, and inside each of the plurality of rings, a single one of the plurality of HVPMOS devices is formed.

20. The structure of claim 17, wherein the heavily doped semiconductor region has an n-type impurity concentration higher than about 1×

10¹⁹/cm³.