Enhanced field Resistive RAM integrated with nanosheet technology

• US 10,504,900 B2
• Filed: 04/23/2018
• Issued: 12/10/2019
• Est. Priority Date: 04/23/2018
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hashemi, Pouya, Ando, Takashi, Reznicek, Alexander
• Primary Examiner(s): Mazumder, Didarul A
• Application Number:
  US15/960,092
• Publication Number:
  US 20190326288A1
• Time in Patent Office: 596 Days
• Field of Search: 257 5
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/34 of the vertical channel field-effect transistor type
• CPC Class Codes: H10N 70/253 having three or more electrodes, e.g. transistor-like devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet CMOS device is provided. In one embodiment, the semiconductor structure includes a gate-all-around nanosheet CMOS device includes a functional gate structure present on, and between, each semiconductor channel material nanosheet of a nanosheet stack of suspended semiconductor channel material nanosheets. The structure of the present application further includes a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device that includes a second functional gate structure present on, and between, each recessed semiconductor channel material layer portion of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each recessed semiconductor channel material layer portion. A shared source/drain region is located between the gate-all-around nanosheet CMOS device and the resistive memory device.

Claims

1. A semiconductor structure comprising:

a gate-all-around nanosheet complementary metal-oxide-semiconductor (CMOS) device comprising a first functional gate structure present on, and between two adjacent semiconductor channel material nanosheets of a nanosheet stack of suspended semiconductor channel material nanosheets;

a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device and comprising a second functional gate structure present on, and between two adjacent recessed semiconductor channel material layer portions of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each of the recessed semiconductor channel material layer portions; and

a shared source/drain (S/D) region located between the gate-all-around nanosheet CMOS device and the resistive memory device.

2. The semiconductor structure of claim 1, wherein an S/D junction is located between each of the semiconductor channel material nanosheets and the shared S/D region, and between each of the recessed semiconductor channel material layer portions and the shared S/D region.

3. The semiconductor structure of claim 1, wherein the recessed semiconductor channel material layer portions have sharp corners that facilitate electroforming of a filament of the resistive memory device.

4. The semiconductor structure of claim 1, wherein each of the recessed semiconductor channel material layer portions has a width that is greater than a width of the sacrificial semiconductor material layer portion.

5. The semiconductor structure of claim 1, further comprising a first gate spacer located above the nanosheet stack of the suspended semiconductor channel material nanosheets and surrounding an upper portion of the first functional gate structure, and an inner spacer surrounding other portions of the first functional gate structure.

6. The semiconductor structure of claim 5, further comprising a second gate spacer located above the material stack and surrounding an upper portion of the second functional gate structure, and an inner spacer surrounding a sidewall of other portions of the second functional gate structure.

7. The semiconductor structure of claim 1, further comprising an S/D region located on a side of the first gate structure not containing the shared S/D region, wherein an S/D junction is present between the S/D region and sidewalls of each of the semiconductor channel material nanosheets.

8. The semiconductor structure of claim 1, further comprising an interlayer dielectric (ILD) material laterally surrounding and present atop the first and second functional gate structures.

9. The semiconductor structure of claim 8, further comprising an S/D contact structure present in the ILD material and directly contacting a topmost surface of the shared S/D region, a first gate contact structure present in the ILD material and directly contacting the first functional gate structure, a second gate contact structure present in the ILD material and directly contacting the second functional gate structure, and a dummy contact structure present in the ILD material and directly contacting a topmost surface of the material stack.

10. The semiconductor structure of claim 1, wherein the semiconductor channel material nanosheets and the recessed semiconductor channel material layer portions comprise a different semiconductor material than the recessed sacrificial semiconductor material layer portion.

11. The semiconductor structure of claim 10, wherein the semiconductor channel material nanosheets and the recessed semiconductor channel material layer portions are composed of silicon and the recessed sacrificial semiconductor material layer portion is composed is a silicon germanium alloy.