Enhanced field Resistive RAM integrated with nanosheet technology
First Claim
1. A semiconductor structure comprising:
- a gate-all-around nanosheet complementary metal-oxide-semiconductor (CMOS) device comprising a first functional gate structure present on, and between two adjacent semiconductor channel material nanosheets of a nanosheet stack of suspended semiconductor channel material nanosheets;
a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device and comprising a second functional gate structure present on, and between two adjacent recessed semiconductor channel material layer portions of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each of the recessed semiconductor channel material layer portions; and
a shared source/drain (S/D) region located between the gate-all-around nanosheet CMOS device and the resistive memory device.
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Accused Products
Abstract
A semiconductor structure containing a resistive random access memory device integrated with a gate-all-around nanosheet CMOS device is provided. In one embodiment, the semiconductor structure includes a gate-all-around nanosheet CMOS device includes a functional gate structure present on, and between, each semiconductor channel material nanosheet of a nanosheet stack of suspended semiconductor channel material nanosheets. The structure of the present application further includes a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device that includes a second functional gate structure present on, and between, each recessed semiconductor channel material layer portion of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each recessed semiconductor channel material layer portion. A shared source/drain region is located between the gate-all-around nanosheet CMOS device and the resistive memory device.
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Citations
11 Claims
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1. A semiconductor structure comprising:
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a gate-all-around nanosheet complementary metal-oxide-semiconductor (CMOS) device comprising a first functional gate structure present on, and between two adjacent semiconductor channel material nanosheets of a nanosheet stack of suspended semiconductor channel material nanosheets; a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device and comprising a second functional gate structure present on, and between two adjacent recessed semiconductor channel material layer portions of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each of the recessed semiconductor channel material layer portions; and a shared source/drain (S/D) region located between the gate-all-around nanosheet CMOS device and the resistive memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification