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Enhanced field Resistive RAM integrated with nanosheet technology

  • US 10,504,900 B2
  • Filed: 04/23/2018
  • Issued: 12/10/2019
  • Est. Priority Date: 04/23/2018
  • Status: Active Grant
First Claim
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1. A semiconductor structure comprising:

  • a gate-all-around nanosheet complementary metal-oxide-semiconductor (CMOS) device comprising a first functional gate structure present on, and between two adjacent semiconductor channel material nanosheets of a nanosheet stack of suspended semiconductor channel material nanosheets;

    a resistive memory device located laterally adjacent to the gate-all-around nanosheet CMOS device and comprising a second functional gate structure present on, and between two adjacent recessed semiconductor channel material layer portions of a material stack, wherein a recessed sacrificial semiconductor material layer portion is located above and below each of the recessed semiconductor channel material layer portions; and

    a shared source/drain (S/D) region located between the gate-all-around nanosheet CMOS device and the resistive memory device.

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