Unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bipolar coercivity

• US 10,504,962 B2
• Filed: 03/28/2016
• Issued: 12/10/2019
• Est. Priority Date: 03/28/2016
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kuo, Charles C., Doczy, Mark L., Oguz, Kaan, O'Brien, Kevin P., Doyle, Brian S.
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US16/069,122
• Publication Number:
  US 20190006417A1
• Time in Patent Office: Days
• Field of Search: 365157, 365158, 365171
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: H10B 61/10 comprising components having two electrodes, e.g. diodes or MIM elements
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details
• CPC Class Codes: H10N 50/85 Magnetic active materials

Abstract

Approaches and structures for unipolar current switching in perpendicular magnetic tunnel junction (pMTJ) devices through reduced bipolar coercivity are described. In an example, a memory array includes a plurality of bitlines and a plurality of select lines. The memory array also includes a plurality of memory elements located among and coupled to the plurality of bitlines and the plurality of select lines. Each of the plurality of memory elements includes a unipolar switching magnetic tunnel junction (MTJ) device and a select device.

Claims

1. A memory array, comprising:

a plurality of bitlines;

a plurality of select lines; and

a plurality of memory elements located among and coupled to the plurality of bitlines and the plurality of select lines, each of the plurality of memory elements comprising a unipolar switching magnetic tunnel junction (MTJ) device and a select device, wherein the select device is a transistor, and wherein only a drain region and not a source region of the transistor is coupled to the unipolar switching MTJ device.

2. The memory element of claim 1, wherein a free magnetic layer of the MTJ device is disposed distal from the drain region of the transistor, and a fixed magnetic layer of the MTJ device is disposed proximate to the drain region of the transistor.

3. The memory array of claim 1, wherein the unipolar switching MTJ device is a unipolar switching perpendicular magnetic tunnel junction (pMTJ) device.

4. A memory element, comprising:

a unipolar switching perpendicular magnetic tunnel junction (pMTJ) device; and

a select device coupled to the pMTJ device, wherein the select device is a transistor, and wherein only a drain region and not a source region of the transistor is coupled to the unipolar switching pMTJ device.

5. The memory element of claim 4, wherein a free magnetic layer of the pMTJ device is disposed distal from the drain region of the transistor, and a fixed magnetic layer of the pMTJ device is disposed proximate to the drain region of the transistor.

6. A method of performing a unipolar switching operation of a magnetic memory element, the method comprising:

applying an increasing negative bias to a magnetic tunnel junction (MTJ) memory element in an initial anti-parallel state; and

, subsequently, changing a resistance of the MTJ memory element from anti-parallel to parallel; and

, subsequently,

further increasing the negative bias to the MTJ element; and

, subsequently, changing the resistance of the MTJ memory element from parallel to anti-parallel, wherein applying the increasing negative bias to the MTJ memory element in the initial anti-parallel state comprises driving with a drain region and not a source region of a select transistor coupled to the MTJ element.

7. The method of claim 6, wherein applying the increasing negative bias to the MTJ memory element in the initial anti-parallel state comprises applying an increasing negative bias to a free magnetic layer of the MTJ memory element.

8. The method of claim 7, wherein applying the increasing negative bias to the free magnetic layer of the MTJ memory element further comprises applying a positive bias to a fixed magnetic layer of the MTJ memory element.

9. The method of claim 6, wherein changing a resistance of the MTJ memory element from parallel to anti-parallel comprises recovering coercivity of the MTJ element.

10. The method of claim 9, further comprising:

subsequent to recovering coercivity of the MTJ element, leaving the MTJ element in a stand-by mode.

11. The method of claim 9, further comprising:

subsequent to recovering coercivity of the MTJ element, performing a read operation of the MTJ element.