Spacers with rectangular profile and methods of forming the same

• US 10,505,018 B2
• Filed: 03/15/2017
• Issued: 12/10/2019
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Yu-Sheng, Lee, Chung-Ju, Bao, Tien-I
• Primary Examiner(s): Hoang, Tuan A
• Application Number:
  US15/459,858
• Publication Number:
  US 20170186616A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02118 carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC polymers per se C08G, photoresist per se G03F
• CPC Class Codes: H01L 21/0212 the material being fluoro carbon compounds, e.g.(CFx) n, (CHxFy) n or polytetrafluoroethylene
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/4983 with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method includes forming a spacer layer on a top surface and sidewalls of a patterned feature, wherein the patterned feature is overlying a base layer, A protection layer is formed to contact a top surface and a sidewall surface of the spacer layer. The horizontal portions of the protection layer are removed, wherein vertical portions of the protect layer remain after the removal. The spacer layer is etched to remove horizontal portions of the spacer layer, wherein vertical portions of the spacer layer remain to form parts of spacers.

Claims

1. A device comprising:

a semiconductor substrate;

a gate stack over the semiconductor substrate;

a gate spacer on a sidewall of the gate stack, wherein the gate spacer comprises;

an inner portion having an inner sidewall contacting the sidewall of the gate stack; and

an outer portion comprising;

an inner edge contacting an outer edge of the inner portion, wherein the inner portion and the outer portion of the gate spacer are formed of different materials, wherein an entirety of the outer portion is offset from the inner portion; and

a bottom surface over and spaced apart from the semiconductor substrate; and

a source/drain region adjacent to the gate spacer, wherein an inner edge of the source/drain region is flushed with an outer edge of the outer portion, and wherein no source/drain extension region exists between the inner edge of the source/drain region and the outer edge of the inner portion of the gate spacer.

2. The device of claim 1, wherein the inner portion of the gate spacer has a bottom surface contacting a top surface of the semiconductor substrate, and wherein the bottom surface of the outer portion of the gate spacer is higher than the bottom surface of the inner portion.

3. The device of claim 2 further comprising a dielectric layer extending from a level higher than a top surface of the gate spacer to a top surface of the source/drain region, wherein the dielectric layer comprises a bottom portion directly underlying the outer portion of the gate spacer.

4. The device of claim 3, wherein the bottom portion of the dielectric layer comprises:

a top surface contacting the bottom surface of the outer portion of the gate spacer; and

a bottom surface in contact with a semiconductor material.

5. The device of claim 1 further comprising:

a dielectric layer contacting the gate spacer, wherein the dielectric layer comprises an Inter-Layer Dielectric (ILD) having portions on opposite sides of a combined region comprising the gate stack and the gate spacer.

6. The device of claim 1, wherein the outer portion of the gate spacer does not overlap the source/drain region, and does not overlap the inner portion.

7. The device of claim 1, wherein both of a top end and a bottom end of the outer edge of the outer portion are directly over, and overlap the inner edge of the source/drain region.

8. A device comprising:

a substrate;

a first gate spacer and a second gate spacer over the substrate;

a gate stack between and contacting the first gate spacer and the second gate spacer;

a first dielectric layer contacting a sidewall of the first gate spacer, wherein the first dielectric layer is vertically spaced apart from the substrate, and an entirety of the first dielectric layer does not overlap the first gate spacer;

a second dielectric layer comprising;

a top portion having a bottom surface contacting a top surface of the first dielectric layer;

a middle portion having a sidewall contacting a sidewall of the first dielectric layer; and

a bottom portion having a top surface contacting a bottom surface of the first dielectric layer, wherein the middle portion is continuously connected to the top portion and the bottom portion with no distinguishable interface therebetween; and

a source/drain region extending into the substrate, wherein an inner edge of the source/drain region is flushed with an outer edge of the first dielectric layer, with the first dielectric layer not overlapping the source/drain region, and the inner edge of the source/drain region is spaced apart from the first gate spacer by a space, and no source/drain extension region is formed in the space.

9. The device of claim 8, wherein the second dielectric layer comprises a contact etch stop layer and an inter-layer dielectric over the contact etch stop layer.

10. The device of claim 8, wherein both of a top end and a bottom end of the outer edge of the first dielectric layer are directly over, and overlap the inner edge of the source/drain region.

11. The device of claim 8, wherein the first gate spacer has a top surface at a first level, and a bottom surface at a second level, and wherein an entirety of the first dielectric layer is between the first level and the second level.

12. The device of claim 8, wherein the bottom portion of the second dielectric layer further comprises a bottom surface contacting a semiconductor material of the substrate.

13. The device of claim 8, wherein the first dielectric layer comprises a carbon-and-nitrogen-containing polymer.

14. The device of claim 8, wherein the first dielectric layer forms a first interface with the first gate spacer, and the bottom portion of the second dielectric layer forms a second interface with the first gate spacer, and the first interface is substantially continuously connected to the second interface.

15. A device comprising:

a semiconductor substrate;

a gate spacer having an outer edge and an inner edge, wherein the outer edge is straight and extends to contact the semiconductor substrate;

a gate stack having an edge contacting the inner edge of the gate spacer;

a first dielectric layer contacting an upper portion of the outer edge of the gate spacer, wherein the first dielectric layer has a bottom higher than a bottom of the outer edge of the gate spacer, and an entirety of the first dielectric layer is formed of a polymer;

a second dielectric layer comprising;

a top portion having a bottom surface contacting a top surface of the first dielectric layer;

a middle portion having a sidewall contacting a sidewall of the first dielectric layer; and

a bottom portion having a top surface contacting a bottom surface of the first dielectric layer, wherein the middle portion is continuously connected to the top portion and the bottom portion with no distinguishable interface therebetween; and

a source/drain region, wherein an inner edge of the source/drain region is flushed with an outer edge of the first dielectric layer, with the first dielectric layer not overlapping the source/drain region, and the inner edge of the source/drain region is spaced apart from the gate spacer by a space, and no source/drain extension region is formed in the space.

16. The device of claim 15, wherein the first dielectric layer has a lengthwise direction parallel to the outer edge of the gate spacer in a cross-sectional view of the device, and wherein a top edge of the first dielectric layer is not higher than a top edge of the gate spacer, and a bottom edge of the first dielectric layer is higher than a bottom edge of the gate spacer.

17. The device of claim 15, wherein the outer edge of the first dielectric layer is straight and overlaps a straight line that extends to overlap the inner edge of the source/drain region.

18. The device of claim 15, wherein the polymer comprises carbon and fluorine.

19. The device of claim 15, wherein both of a top end and a bottom end of the outer edge of the first dielectric layer are directly over, and overlap the inner edge of the source/drain region.

20. The device of claim 15, wherein the first dielectric layer and the second dielectric layer form a distinguishable vertical interface therebetween.