Semiconductor device including a shoulder portion and manufacturing method

• US 10,505,028 B2
• Filed: 09/05/2016
• Issued: 12/10/2019
• Est. Priority Date: 09/16/2015
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Naito, Tatsuya
• Primary Examiner(s): Huber, Robert T
• Application Number:
  US15/256,634
• Publication Number:
  US 20170077274A1
• Time in Patent Office: 1,191 Days
• Field of Search: 257143
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/083 Anode or cathode regions of thyristors or gated bipolar-mode devices
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

A semiconductor device including a semiconductor substrate; a trench formed in a front surface of the semiconductor substrate; a gate conducting portion formed within the gate trench; and a first region formed adjacent to the trench in the front surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate. A shoulder portion is provided on a side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the gate trench at a position opposite the top end of the gate conducting portion, and a portion of the first region that contacts the gate trench is formed as a deepest portion thereof.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a gate trench that is formed in a front surface of the semiconductor substrate and is provided extending in a predetermined extension direction in the front surface of the semiconductor substrate;

a gate conducting portion that is formed within the gate trench, provided such that a top end thereof is at a deeper position than the front surface of the semiconductor substrate, and insulated from the semiconductor substrate;

a plurality of first regions and a plurality of second regions, provided in an alternating manner in the extension direction in a region adjacent to the gate trench in the front surface of the semiconductor substrate, each of the first regions having a higher impurity concentration than the semiconductor substrate, each of the second regions having a different conduction type than the first region, and

a third region that is formed on the back surface side of each of the first regions and the second regions and has a different conduction type than the first regions, wherein

a plurality of shoulder portions are provided respectively in both a side wall of the gate trench adjacent to the first region and a side wall of the gate trench adjacent to the second region, and each of the shoulder portions is provided on the corresponding side wall of the gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the corresponding side wall of the gate trench at a position opposite the top end of the gate conducting portion,

each of the first regions and the second regions includes a side surface in direct contact with the gate trench, and a bottom surface that intersects with the side surface, the intersection of the side surface and the bottom surface provided at a position deeper than other portions of the bottom surface,

an intersection of the bottom surface of the second region and the side surface adjacent to the gate trench is deeper than the intersection of the bottom surface of the first region and the side surface adjacent to the gate trench,

a bottom surface of the second region at a center between the gate trench and an adjacent gate trench is deeper than the bottom surface of the first region at a center between the gate trench and an adjacent gate trench, and

a length difference D7 between a depth at the intersection of the bottom surface of the second region and a depth at the intersection of the bottom surface of the first region is greater than a length difference D4 between a depth at the bottom surface of the second region at the center between the gate trench and the adjacent gate and a depth at the bottom surface of the first region at the center between the gate trench and the adjacent gate.

2. The semiconductor device according to claim 1, wherein

each of the shoulder portions has a convex curved surface portion that protrudes toward the inside of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein

a portion of each of the first regions and the second regions contacting the gate trench is a longest portion of the corresponding first region and the corresponding second region in the depth direction.

4. The semiconductor device according to claim 1, wherein

a portion of an end surface of the gate conducting portion on the front surface side of the semiconductor substrate that is adjacent to the side wall of the gate trench is a portion of the end surface of the gate conducting portion formed closest to the front surface of the semiconductor substrate.

5. The semiconductor device according to claim 1, wherein

the side wall of the gate trench has a portion forming an angle greater than or equal to 20 degrees relative to the depth direction of the semiconductor substrate at each of the shoulder portions.

6. The semiconductor device according to claim 1, wherein the intersection of the side surface and the bottom surface is the deepest position of the bottom surface of the corresponding first region and the corresponding second region directly below the shoulder portion.

7. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is directly below the shoulder portion, and

a depth of the bottom surface decreases from the side surface away from the gate trench.

8. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is directly below the shoulder portion, and

the bottom surface slopes upward from the intersection of the side surface and the bottom surface.

9. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is provided between the gate trench and an adjacent gate trench, and

a depth of the intersection of the side surface and the bottom surface is greater than a depth of the bottom surface at a midpoint between the gate trench and the adjacent gate trench.

10. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is provided between the gate trench and an adjacent gate trench, and

each of the bottom surfaces of the corresponding first region and the corresponding second region becomes deeper starting from a midpoint between the gate trench and the adjacent gate trench to the intersection of the side surface and the bottom surface.

11. The semiconductor device according to claim 1, wherein

a length of each of the first regions and the second regions in a depth direction is greatest at the side surface of the corresponding first region and the corresponding second region.

12. The semiconductor device according to claim 1, wherein

a top surface of the gate conducting portion includes a downward slope inward from the side wall to a center of the gate trench.

13. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is provided between the gate trench and an adjacent gate trench, and

a length in a depth direction of each of the first regions and the second regions in the shoulder portion is greater than a length of the corresponding first region and the corresponding second region at a midpoint between the gate trench and the adjacent gate trench.

14. The semiconductor device according to claim 1, wherein

the first regions and second regions are provided between corresponding gate trenches and corresponding adjacent gate trenches, and

a length difference in a depth direction between the first regions and the second regions in the shoulder portion is greater than a length difference between the first regions and the second regions at a midpoint between the gate trench and the adjacent gate trench.

15. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is provided between the gate trench and an adjacent gate trench, and

the semiconductor device further comprises an emitter electrode that is in direct contact with the first regions and the second regions provided between the gate trench and the adjacent gate trench on the front surface of the semiconductor substrate.

16. The semiconductor device according to claim 1, wherein

each of the first regions and the second regions is a continuous layer extending between the gate trench and an adjacent gate trench.

17. A semiconductor device comprising:

a semiconductor substrate;

a first gate trench that is formed in a front surface of the semiconductor substrate;

a gate conducting portion that is formed within the first gate trench, provided such that a top end thereof is at a deeper position than the front surface of the semiconductor substrate, and insulated from the semiconductor substrate; and

a first region that is formed adjacent to the first gate trench in the front surface of the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate, wherein

a shoulder portion is provided on a side wall of the first gate trench between the top end of the gate conducting portion and the front surface of the semiconductor substrate and has an average slope, relative to a depth direction of the semiconductor substrate, that is greater than a slope of the side wall of the first gate trench at a position opposite the top end of the gate conducting portion, and

the first region includes a side surface in direct contact with the first gate trench, and a bottom surface that intersects with the side surface, the intersection of the side surface and the bottom surface provided at a position deeper than other portions of the bottom surface, wherein

a second gate trench having a larger distance from the front surface of the semiconductor substrate to a top end of a corresponding gate conducting portion than that of the first gate trench is formed in the semiconductor substrate,

an intersection of the bottom surface of the first region and a side surface adjacent to the second gate trench is deeper than the intersection of the bottom surface of the first region and the side surface adjacent to the first gate trench.

18. The semiconductor device according to claim 17, wherein

the semiconductor substrate further includes a third region that is formed on the back surface side of each of the first regions, has a different conduction type than the first regions, and has a bottom end with a uniform depth.

19. The semiconductor device according to claim 17, wherein

the first gate trench is provided extending in a predetermined extension direction in the front surface of the semiconductor substrate,

the first region is provided along the extension direction in a region adjacent to the first gate trench in the front surface of the semiconductor substrate, and

the semiconductor device further comprises:

a third region that is formed below the first region in the semiconductor substrate and has a different conduction type than the first region;

a plug that penetrates through the first region and has a bottom end arranged within the third region; and

a second region that is formed in contact with the bottom end of the plug in the third region, has the same conduction type as the third region, and has a higher impurity concentration than the third region.

20. The semiconductor device according to claim 19, further comprising:

an accumulation region that is formed below the third region in the semiconductor substrate and has a higher impurity concentration than the semiconductor substrate.

21. The semiconductor device according to claim 17, wherein

a distance L1 from the front surface of the semiconductor substrate to the top end of the gate conducting portion of the first gate trench is smaller than a distance L2 from the front surface of the semiconductor substrate to the top end of the gate conducting portion of the second gate trench.