Electronic device of vertical MOS type with termination trenches having variable depth

• US 10,505,033 B2
• Filed: 04/05/2017
• Issued: 12/10/2019
• Est. Priority Date: 01/29/2014
• Status: Active Grant

• Current Assignee: STMicroelectronics International N.V. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Magri, Angelo, Barletta, Giacomo
• Primary Examiner(s): Tran, Dzung
• Application Number:
  US15/479,975
• Publication Number:
  US 20170207334A1
• Time in Patent Office: 979 Days
• Field of Search: 257330, 257737
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/063 Reduced surface field [RESURF] pn-junction structures
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

An electronic device is integrated on a chip of semiconductor material having a main surface and a substrate region with a first type of conductivity. The electronic device has a vertical MOS transistor, formed in an active area having a body region with a second conductivity type. A set of one or more cells each one having a source region of the first conductivity, a gate region of electrically conductive material in a gate trench extending from the main surface in the body region and in the substrate region, and an insulating gate layer, and a termination structure with a plurality of termination rings surrounding at least part of the active area on the main surface, each termination ring having a floating element of electrically insulating material in the termination trench extending from the main surface in the chip and at least one bottom region of said semiconductor material of the second conductivity type extending from at least one deepest portion of a surface of the termination trench in the chip; the termination trenches have a depth from the main surface decreasing moving away from the active area.

Claims

1. A method, comprising:

forming an active area in a substrate;

forming a termination structure area in the substrate, the termination structure surrounding the active area;

forming a transistor in the active area; and

forming a plurality of termination trenches in the termination structure area, forming the plurality of termination trenches including;

forming a first termination trench of the plurality of termination trenches in the substrate, the first termination trench having a first width and extending in to the substrate to a first depth;

filling an entirety of the first termination trench with an electrically insulating material; and

forming a second termination trench of the plurality of termination trenches in the substrate, the second termination trench having a second width and extending in to the substrate to a second depth, the first width being larger than the second width, the first depth being larger than the second depth, the first termination trench and the second termination trench being spaced from each other by substantially equal distances.

2. The method of claim 1 wherein the forming the plurality of termination trenches further includes:

forming a masking layer on the substrate;

forming a photo-resist layer on the masking layer;

forming first and second openings in the photo-resist layer, the first opening being larger than the second opening; and

forming third and fourth openings in the masking layer, the third and fourth openings being aligned with the first and second openings, respectively, the first termination trench being formed through the first and third openings, the second termination trench being formed through the second and fourth openings.

3. The method of claim 2 wherein forming the plurality of termination trenches further includes removing the masking layer and the photo-resist layer subsequent to forming the first and second termination trenches.

4. The method of claim 1 wherein forming the plurality of termination trenches further includes forming a doped bottom region in the first termination trench by performing an implantation operation in a direction that is substantially parallel to a surface of the substrate.

5. The method of claim 4 wherein forming the plurality of termination trenches further includes forming a doped side region in the first termination trench by performing an implantation operation in a direction that is angled relative to the direction that is substantially parallel to a surface of the substrate.

6. The method of claim 5 wherein the electrically insulating material filling the entirety of the first termination trench is separated from the substrate by the doped bottom region and the doped side region.

7. A device, comprising:

a substrate having an active area and a termination structure area surrounding the active area; and

a plurality of termination trenches in the termination structure area, the plurality of termination trenches extending through a surface of the substrate, the plurality of termination trenches having widths that are different from each other and being spaced from each other by substantially equal distances, each of the plurality of termination trenches including;

a doped bottom region;

a doped side region that extends from the doped bottom region to the surface of the substrate; and

an electrically insulating material filling the entire termination trench between the surface of the substrate and the doped bottom region.

8. The device of claim 7 wherein the electrically insulating material is separated from the substrate by the doped bottom region and the doped side region.

9. The device of claim 7 wherein the plurality of termination trenches includes a first termination trench that has a first width and extends in to the substrate to a first depth, and a second termination trench that has a second width and extends in to the substrate to a second depth, the first width being larger than the second width, the first depth being larger than the second depth.

10. The device of claim 7, further comprising a field oxide layer on the substrate, the field oxide layer overlying at least one of the plurality of termination trenches.

11. The device of claim 10, further comprising a conductive layer extending from the active area to the termination structure area, the conductive layer overlying the plurality of termination trenches.

12. The device of claim 7 wherein a depth of each of the plurality of termination trenches decreases as each of the plurality of termination trenches is further away from the active area.

19. The device of claim 7, further comprising an electrically insulating protection layer on the surface of the substrate, the electrically insulating protection layer in direct contact with and covering the electrically insulating material filling the termination trenches.

20. The device of claim 7 wherein the doped side regions of adjacent ones of the termination trenches are spaced apart from one another at the surface of the substrate.

13. A device, comprising:

a substrate;

an active area in the substrate;

a termination structure area in the substrate, the termination structure surrounding the active area;

a transistor in the active area;

a plurality of termination trenches in the termination structure area, the plurality of termination trenches including;

a first termination trench in the substrate, the first termination trench having a first width and extending in to the substrate to a first depth; and

a second termination trench in the substrate, the second termination trench having a second width and extending in to the substrate to a second depth, the first width being larger than the second width, the first depth being larger than the second depth, the first termination trench and the second termination trench being spaced from each other by substantially equal distances; and

a dielectric material completely filling each of the plurality of termination trenches.

14. The device of claim 13, further comprising:

a first oxide layer on the substrate, the first oxide layer positioned between the plurality of termination trenches and an edge of substrate.

15. The device of claim 14, further comprising:

a second oxide layer on the plurality of termination trenches and the substrate, the first oxide layer being formed on the second oxide layer.

16. The device of claim 14, further comprising:

a conductive layer on the first oxide layer.

17. The device of claim 13, further comprising:

a source electrode on the substrate, the source electrode extending from the transistor, over the plurality of termination trenches, and to a position between the plurality of termination trenches and an edge of the substrate.

18. The device of claim 17, further comprising:

a gate electrode on the substrate, the gate electrode positioned between the source electrode and the edge of the substrate.