Fusion bonded liquid crystal polymer electrical circuit structure

• US 10,506,722 B2
• Filed: 03/15/2016
• Issued: 12/10/2019
• Est. Priority Date: 07/11/2013
• Status: Active Grant

• Current Assignee: LCP Medical Technologies Incorporated
• Original Assignee: HSIO Technologies LLC
• Inventors: Rathburn, James J.
• Primary Examiner(s): Vo, Peter Dungba
• Assistant Examiner(s): Parvez, Azm A
• Application Number:
  US15/070,026
• Publication Number:
  US 20160212862A1
• Time in Patent Office: 1,365 Days
• Field of Search: 29831, 29829, 29825, 295921
• CPC Class Codes: C23C 18/1603 coating on selected surface areas
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/38 Coating with copper
• CPC Class Codes: C25D 3/38 of copper
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/0393 Flexible materials H05K1/038 takes precedence; specific organic compositions are classified in H05K1/0313 and subgroups
• CPC Class Codes: H05K 2201/0141 Liquid crystal polymer [LCP]
• CPC Class Codes: H05K 2201/09563 Metal filled via plated through-hole filled with insulating material H05K2201/0959
• CPC Class Codes: H05K 3/421 Blind plated via connections H05K3/422, H05K3/423 and H05K3/425 take precedence
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: H05K 3/4623 the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards H05K3/462 takes precedence
• CPC Class Codes: H05K 3/4635 laminating flexible circuit boards using additional insulating adhesive materials between the boards
• CPC Class Codes: H05K 3/4679 Aligning added circuit layers or via connections relative to previous circuit layers
• CPC Class Codes: Y10T 29/49128 : Assembling formed circuit to base

Abstract

A method of making a fusion bonded circuit structure. A substrate is provided with a seed layer of a conductive material. A first resist layer is deposited on the seed layer. The first resist layer is processed to create first recesses corresponding to a desired first circuitry layer. The first recesses expose, portions of the seed layer of conductive material. The substrate is electroplated to create first conductive traces defined by the first recesses. The first resist layer is removed to reveal the first conductive traces. The substrate is etched to remove exposed portions of the seed layer adjacent the first conductive traces. A portion of the seed layer is interposed between the first conductive traces and the substrate. A first layer of LCP is fusion boned to the first major surface of the substrate to encapsulate the first conductive traces in an LCP material. The first LCP layer can be laser drilled to expose the conductive traces.

Claims

1. A method of making a fusion bonded circuit structure comprising the step of:

providing a first substrate with a first major surface having a seed layer of a conductive material;

depositing a first resist layer on the seed layer of conductive material;

processing the first resist layer to create a plurality of first recesses corresponding to a desired first circuitry layer, the first recesses exposing portions of the seed layer of conductive material;

electroplating the first substrate to create first conductive traces defined by the first recesses, wherein the seed layer of conductive material acts as an electrical bus for the electroplating process;

removing the first resist layer to reveal the first conductive traces;

etching the first substrate to remove exposed portions of the seed layer of conductive material adjacent the first conductive traces, wherein an unetched portion of the seed layer of conductive material remains between the first conductive traces and the first substrate;

fusion bonding a first liquid polymer layer (“

LCP”

) layer to the first major surface of the first substrate to encapsulate the first conductive traces in an LCP material;

forming a plurality of first vias through the first LCP layer to the first conductive traces;

bulk plating the plurality of first vias with a conductive material to form a plurality of first conductive pillars of solid metal;

laser drilling the first LCP layer to expose contact pads for the first conductive traces;

positioning a second LCP substrate containing a second circuitry layer opposite the first conductive pillars; and

fusion bonding the second LCP substrate to the first LCP layer to electrically couple the first conductive pillars to the second circuitry layer and to encapsulate the first conductive pillars and the second circuitry layer in an LCP material.

2. The method of claim 1 wherein the step of depositing the first resist layer comprises the steps of:

depositing the first resist layer as a liquid; and

imaging the first resist layer to create the first recesses.

3. The method of claim 1 wherein the first conductive traces comprise a pitch of about 25 microns.

4. The method of claim 1 wherein the first conductive traces comprise a thickness of about 20 microns to about 50 microns.

5. The method of claim 1 wherein the first conductive traces comprise a generally rectangular cross-sectional shape.

6. The method of claim 1 comprising the step of planarizing the first conductive traces before the step of removing the first resist layer.

7. The method of claim 1 comprising the steps of:

laser drilling the plurality of first vias through the first LCP layer to the first conductive traces; and

bulk plating the plurality of first vias with a conductive material to form a plurality of conductive pillars of solid metal that substantially fill the vias.

8. The method of claim 7 comprising the steps of:

preparing inside surfaces of one or more of the first vias to receive electro-less plating; and

electro-less plating one or more of the first vias before plating the conductive pillars.

9. The method of claim 7 comprising the steps of:

attaching a second circuitry layer to a first major surface of the first substrate; and

electrically coupling the conductive pillars to the second circuitry layer.

10. The method of claim 9 comprising the steps of:

bonding a second LCP layer to an exposed surface of the second circuitry layer, and

laser drilling a plurality of second vias through the second LCP layer to the second circuitry layer.

11. The method of claim 1 comprising the steps of:

laser drilling the plurality of first vias through the first LCP layer to the first conductive traces; and

barrel plating the first vias.

12. The method of claim 1 wherein the seed layer of the conductive material is about 3 microns to about 5 microns thick.

13. The method of claim 1 comprising the step of electroplating the first recesses to a top surface of the first resist layer.

14. The method of claim 1 comprising the step of applying electro-less plating to sidewalls of the first recesses before the electroplating step.

15. A method of making a fusion bonded circuit structure comprising the step of:

providing a first substrate with a first major surface having a seed layer of a conductive material;

depositing a first resist layer on the seed layer of conductive material;

processing the first resist layer to create a plurality of first recesses corresponding to a plurality of first vias openings, the first vias openings exposing portions of the seed layer of conductive material;

electroplating the first substrate to create first conductive pillars defined by the first vias openings, wherein the seed layer of conductive material acts as an electrical bus for the electroplating process;

removing the first resist layer to reveal the first conductive pillars;

etching the first substrate to remove exposed portions of the seed layer of conductive material adjacent the first conductive pillars, wherein an unetched portion of the seed layer of conductive material remains between the first conductive pillars and the first substrate;

fusion bonding a first liquid crystal polymer (“

LCP”

) layer to the first major surface of the first substrate to encapsulate the first conductive pillars in an LCP material;

forming a plurality of second vias through the first LCP layer to the conductive pillars;

bulk plating the plurality of second vias with a conductive material to form a plurality of second conductive pillars of solid metal;

laser drilling the first LCP layer to expose a plurality of the first conductive pillars;

positioning a second LCP substrate containing a second circuitry layer opposite the second conductive pillars; and

fusion bonding the second LCP substrate to the first LCP layer to electrically couple the second conductive pillars to the second circuitry layer and to encapsulate the second conductive pillars and the second circuitry layer in an LCP material.

16. The method of claim 15 wherein the conductive pillars comprise a diameter in the range of about 25 microns to about 50 microns.