Timing-aware test generation and fault simulation

• US 10,509,073 B2
• Filed: 07/31/2017
• Issued: 12/17/2019
• Est. Priority Date: 04/27/2006
• Status: Active Grant

• Current Assignee: Mentor Graphics Corporation (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Lin, Xijiang, Tsai, Kun-Han, Kassab, Mark, Wang, Chen, Rajski, Janusz
• Primary Examiner(s): Nguyen, Steve N
• Application Number:
  US15/664,169
• Publication Number:
  US 20180045780A1
• Time in Patent Office: 869 Days
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318328 for delay tests
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318357 Simulation computer simulation of digital circuits G06F30/3308
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30

Abstract

Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

Claims

1. A method of generating test patterns for testing an integrated circuit, comprising:

identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;

computing a static path delay for a selected sensitized path through the identified fault;

determining whether a criterion based at least in part on the static path delay is met for the identified fault;

modifying a fault list by removing the identified fault if the criterion is met; and

storing the modified fault list,

wherein either;

(a) the selected sensitized path is the longest sensitized path, and the act of determining whether the criterion is met comprises determining whether;

2. The method of claim 1, wherein the criterion is a first criterion, and wherein the method further comprises:

computing an actual path delay for the selected sensitized path through the identified fault;

determining whether a second criterion based at least in part on the actual path delay is met for the identified fault; and

modifying the fault list by removing the identified fault if the first criterion is not met but the second criterion is met.

3. The method of claim 2, wherein the act of determining whether the second criterion is met comprises determining whether:

4. The method of claim 2, wherein the act of determining whether the second criterion is met comprises determining whether:

5. The method of claim 1, wherein the method is repeated for additional faults in the fault list not detected by previously generated test patterns.

6. One or more non transitory computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising:

identifying a fault that is detected by a test pattern by simulating a response of an integrated circuit design to the test pattern in the presence of the fault and identifying one or more paths that are sensitized by the test pattern and that detect the fault;

computing a static path delay for a selected sensitized path through the identified fault;

determining whether a criterion based at least in part on the static path delay is met for the identified fault;

modifying a fault list by removing the identified fault if the criterion is met; and

storing the modified fault list, and

wherein either;

(a) the selected sensitized path is the longest sensitized path, and the act of determining whether the criterion is met comprises determining whether;

7. One or more computer-readable media storing a fault list created by the method of claim 6.

8. The one or more computer-readable media of claim 6, wherein the criterion is a first criterion, and wherein the method further comprises:

computing an actual path delay for the selected sensitized path through the identified fault;

determining whether a second criterion based at least in part on the actual path delay is met for the identified fault; and

modifying the fault list by removing the identified fault if the first criterion is not met but the second criterion is met.

9. The one or more computer-readable media of claim 8, wherein the act of determining whether the second criterion is met comprises determining whether:

10. The one or more computer-readable media of claim 6, wherein the method is repeated for additional faults in the fault list not detected by previously generated test patterns.

11. The one or more computer-readable media of claim 8, wherein the act of determining whether the second criterion is met comprises determining whether: