Low standby power with fast turn on method for non-volatile memory devices

• US 10,510,387 B2
• Filed: 08/06/2018
• Issued: 12/17/2019
• Est. Priority Date: 08/31/2015
• Status: Active Grant

• Current Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Original Assignee: Longitude Flash Memory Solutions, Ltd. (Vector Capital Corporation)
• Inventors: Zonte, Cristinel, Raghavan, Vijay, Gradinariu, Iulian, Moscaluk, Gary Peter, Bettman, Roger Jay, Argrawal, Vineet, Leshner, Samuel
• Primary Examiner(s): Pham, Ly D
• Application Number:
  US16/055,570
• Publication Number:
  US 20190080732A1
• Time in Patent Office: 498 Days
• Field of Search: 36518523
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/148 Details of power up or power down circuits, standby circuits or recovery circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.

Claims

1. A method comprising:

detecting a standby condition of a non-volatile memory system;

reducing bias currents provided to driving circuits of the non-volatile memory system in response to detecting the standby condition;

operating the non-volatile memory system in a standby mode after the bias currents have been reduced, wherein operating the non-volatile memory system in the standby mode comprises maintaining an output signal indicating the standby mode until a read instruction is detected;

detecting the read instruction to the non-volatile memory system;

increasing the bias currents provided to the driving circuits in response to detecting the read instruction; and

changing the output signal to indicate an active mode when the read instruction is detected.

2. The method of claim 1, wherein detecting the standby condition comprises determining that the non-volatile memory system is not in a wake-up mode.

3. The method of claim 1, wherein detecting the standby condition comprises determining that the non-volatile memory system is not in a start-up mode.

4. The method of claim 1, wherein detecting the standby condition occurs after a lapse in time since the last read request to the non-volatile memory system.

5. The method of claim 4, wherein the lapse in time corresponds to the receipt or absence of a number of clock cycles.

6. The method of claim 5, wherein the lapse in time is at least one clock cycle.

7. The method of claim 1, further comprising:

detecting the read instruction to the non-volatile memory system; and

increasing the bias currents provided to the driving circuits in response to detecting the read instruction.

8. The method of claim 7, further comprising changing the output signal to indicate an active mode when the read instruction is detected.