Method, flash memory controller, memory device for accessing 3D flash memory having multiple memory chips
First Claim
1. A method for accessing a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages;
- and the method comprises;
configuring and planning the flash memory chips so that the flash memory chips include at least one super block; and
allocating a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;
wherein each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;
all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;
all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and
, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set.
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Abstract
A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.
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Citations
15 Claims
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1. A method for accessing a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages;
- and the method comprises;
configuring and planning the flash memory chips so that the flash memory chips include at least one super block; and allocating a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block; wherein each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;
all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;
all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and
, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set. - View Dependent Claims (2, 3, 4, 5, 6, 7)
- and the method comprises;
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8. A flash memory controller for accessing a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages, and the flash memory controller comprises:
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a memory, configured for storing a program code; a microprocessor, configured for executing the program code to control access of the flash memory module; and a codec; wherein the microprocessor configures and plans the flash memory chips so that the flash memory chips include at least one super block, and allocates a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;
each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;
all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;
all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and
, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A memory device, comprising:
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a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages; and a flash memory controller, configured for accessing the flash memory module; wherein the flash memory controller is arranged for configuring and planning the flash memory chips so that the flash memory chips include at least one super block, and for assigning a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;
each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;
all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;
all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and
, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set.
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Specification