Method, flash memory controller, memory device for accessing 3D flash memory having multiple memory chips

• US 10,510,430 B2
• Filed: 05/15/2018
• Issued: 12/17/2019
• Est. Priority Date: 04/27/2016
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion Technology Corporation)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion Technology Corporation)
• Inventors: Yang, Tsung-Chieh, Hsu, Hong-Jung
• Primary Examiner(s): Nguyen, Vanthu T
• Application Number:
  US15/979,467
• Publication Number:
  US 20180260322A1
• Time in Patent Office: 581 Days
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.

Claims

1. A method for accessing a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages;

and the method comprises;

configuring and planning the flash memory chips so that the flash memory chips include at least one super block; and

allocating a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;

wherein each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;

all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;

all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and

, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set.

2. The method of claim 1, wherein the buffer memory space is dedicated to store temporary parity check codes generated during an encoding procedure of programming any data into the at least one super block.

3. The method of claim 1, wherein the at least one super block includes a multiple-level cell block of each flash memory chip among the flash memory chips.

4. The method of claim 3, wherein the multiple-level cell blocks are TLC blocks or QLC blocks.

5. The method of claim 1, further comprising:

during programming the data into the at least one super block;

reading a portion of the data, which has been written into the at least one super block, from the at least one super block;

reading at least one portion of parity check codes from the buffer memory; and

using the at least one portion of parity check codes to perform error correction upon the portion of the data when an error occurs and cannot corrected during reading the portion of the data.

6. The method of claim 1, further comprising:

reading the multiple sets of temporary parity check codes from the buffer memory space;

encoding the multiple sets of temporary parity check codes to generate a set of final parity check codes; and

programming the set of final parity check codes into the at least one super block.

7. The method of claim 6, further comprising:

after programming the set of final parity check codes into the at least one super block;

reading a portion of the data from the at least one super block; and

reading the set of final parity check codes from the at least one super block, and using the set of final parity check codes to perform error correction upon the portion of the data when an error occurs and cannot corrected during reading the portion of the data.

8. A flash memory controller for accessing a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages, and the flash memory controller comprises:

a memory, configured for storing a program code;

a microprocessor, configured for executing the program code to control access of the flash memory module; and

a codec;

wherein the microprocessor configures and plans the flash memory chips so that the flash memory chips include at least one super block, and allocates a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;

each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;

all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;

all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and

, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set.

9. The flash memory controller of claim 8, wherein the buffer memory space is dedicated to store temporary parity check codes generated during an encoding procedure of programming any data into the at least one super block.

10. The flash memory controller of claim 8, wherein the at least one super block includes a multiple-level cell block of each flash memory chip among the flash memory chips.

11. The flash memory controller of claim 10, wherein the multiple-level cell blocks are TLC blocks or QLC blocks.

12. The flash memory controller of claim 8, wherein during programming the data into the at least one super block, the microprocessor is arranged for:

reading a portion of the data, which has been written into the at least one super block, from the at least one super block;

reading at least one portion of parity check codes from the buffer memory; and

using the at least one portion of parity check codes to perform error correction upon the portion of the data when an error occurs and cannot corrected during reading the portion of the data.

13. The flash memory controller of claim 8, wherein the microprocessor is arranged for:

reading the multiple sets of temporary parity check codes from the buffer memory space;

encoding the multiple sets of temporary parity check codes to generate a set of final parity check codes; and

programming the set of final parity check codes into the at least one super block.

14. The flash memory controller of claim 13, wherein after programming the set of final parity check codes into the at least one super block, the microprocessor is arranged for:

reading a portion of the data from the at least one super block; and

reading the set of final parity check codes from the at least one super block, and using the set of final parity check codes to perform error correction upon the portion of the data when an error occurs and cannot corrected during reading the portion of the data.

15. A memory device, comprising:

a flash memory module being a 3D flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages; and

a flash memory controller, configured for accessing the flash memory module;

wherein the flash memory controller is arranged for configuring and planning the flash memory chips so that the flash memory chips include at least one super block, and for assigning a buffer memory space for storing multiple sets of temporary parity check codes generated by an encoding procedure during programming data into the at least one super block;

each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes;

all word lines disposed on a same 3D stacked plane are classified into a same word line set, and word lines on different 3D stacked planes are respectively classified into different word line sets;

all word line sets on the different 3D stacked planes are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and

, at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets, the different non-adjacent word line sets comprising odd and even word lines of a first word line set and odd and even word lines of a second word line set that is not adjacent to the first word line set.