Hydrogenation and nitridization processes for modifying effective oxide thickness of a film

• US 10,510,545 B2
• Filed: 01/09/2019
• Issued: 12/17/2019
• Est. Priority Date: 06/20/2016
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Graoui, Houda, Swenberg, Johanes S., Liu, Wei, Hung, Steven C. H.
• Primary Examiner(s): Chang, Jay C
• Assistant Examiner(s): Liu, Mikka
• Application Number:
  US16/244,051
• Publication Number:
  US 20190172716A1
• Time in Patent Office: 342 Days
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/28512 on semiconductor bodies comprising elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 21/28575 on semiconductor bodies comprising AIIIBV compounds
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/452 on AIII-BV compounds

Abstract

Embodiments described herein generally relate to enable the formation of a metal gate structure with a reduced effective oxide thickness over a similar structure formed via conventional methods. A plasma hydrogenation process followed by a plasma nitridization process, or a single-step plasma hydrogenation and nitridization process, is performed on a metal nitride layer in a film stack, thereby, according to some embodiments, removing oxygen atoms disposed within layers of the film stack and, in some embodiments, adding nitrogen atoms to the layers of the film stack. As a result, an effective oxide thickness of the metal gate structure is reduced with little or no accompanying flatband voltage shift.

Claims

1. A method of forming a structure in a semiconductor device, the method comprising:

depositing a metal nitride capping layer on a high-k dielectric layer formed over a surface of a substrate;

exposing an exposed surface of the deposited metal nitride capping layer to a plasma that comprises a first gas that comprises a hydrogen containing species and a second gas that comprises a nitrogen containing species, wherein the hydrogen containing species in the first gas comprises nitrogen;

depositing a silicon-containing layer on the exposed surface of the deposited metal nitride capping layer after exposing the exposed surface to the plasma;

performing a thermal anneal process on the silicon-containing layer; and

removing the silicon-containing layer.

2. The method of claim 1, wherein the metal nitride capping layer comprises a metal selected from a group consisting of titanium, tantalum and tungsten.

3. The method of claim 1, wherein a substrate bias is applied to the substrate while exposing the exposed surface to the plasma.

4. The method of claim 1, further comprising:

forming a silicon dioxide containing interface layer on the surface of the substrate,

wherein the high-k dielectric layer is formed on the silicon dioxide containing interface layer formed on the substrate.

5. The method of claim 1, wherein the exposing an exposed surface is performed in a process chamber, and the method further comprising, prior to the exposing an exposed surface, performing an oxygen-free plasma treatment process on at least one surface of the process chamber in which the exposed surface is exposed to the plasma that comprises the first gas that comprises the hydrogen containing species and the second gas that comprises the nitrogen containing species, and wherein the substrate is not disposed within the process chamber during the performing an oxygen-free plasma treatment.

6. The method of claim 1, wherein the metal nitride capping layer comprises titanium and nitrogen, the hydrogen containing species comprises ammonia, and the nitrogen containing species comprises nitrogen gas (N₂).

7. The method of claim 1, wherein the hydrogen containing species comprises ammonia, and the nitrogen containing species comprises nitrogen gas (N₂).

8. The method of claim 7, wherein the exposing an exposed surface further comprises exposing the exposed surface to argon (Ar).

9. A method of forming a structure in a semiconductor device, the method comprising:

depositing a metal nitride capping layer on a high-k dielectric layer formed over a surface of a substrate;

exposing an exposed surface of the deposited metal nitride capping layer to a plasma that comprises a first gas that comprises a hydrogen containing species and a second gas that comprises a nitrogen containing species, wherein the hydrogen containing species in the first gas comprises nitrogen;

depositing a sacrificial layer on the high-k dielectric layer;

depositing a silicon-containing layer on the sacrificial layer;

performing a thermal anneal process on the sacrificial layer and the silicon-containing layer; and

removing the sacrificial layer and the silicon-containing layer before depositing a metal nitride capping layer on the high-k dielectric layer.

10. A method of forming a structure in a semiconductor device, the method comprising:

depositing a high-k dielectric layer on a semiconductor substrate;

depositing on the high-k dielectric layer a capping layer;

exposing an exposed surface of the capping layer to a plasma-excited hydrogen species and a plasma-excited nitrogen species;

exposing the exposed surface to air;

performing a thermal anneal process on the high-k dielectric layer and the capping layer for a particular time and at a particular temperature;

depositing a silicon-containing layer on the exposed surface;

performing a secondary thermal anneal process on the silicon-containing layer; and

removing the silicon-containing layer.

11. The method of claim 10, wherein the capping layer comprises nitrogen and a metal.

12. The method of claim 11, wherein the capping layer comprises titanium (Ti).

13. The method of claim 10, further comprising, prior to depositing the high-k dielectric layer, forming a silicon dioxide containing interface layer on which the high-k dielectric layer is subsequently formed.

14. The method of claim 10, wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface to the plasma-excited hydrogen species and the plasma-excited nitrogen species.

15. A method of forming a structure in a semiconductor device, the method comprising:

depositing a high-k dielectric layer on a semiconductor substrate;

depositing on the high-k dielectric layer a capping layer;

exposing an exposed surface of the capping layer to a plasma-excited hydrogen species and a plasma-excited nitrogen species;

exposing the exposed surface to air;

performing a thermal anneal process on the high-k dielectric layer and the capping layer for a particular time and at a particular temperature;

depositing a sacrificial layer on the high-k dielectric layer;

depositing a silicon-containing layer on the sacrificial layer;

performing a tertiary thermal anneal process on the sacrificial layer and the silicon-containing layer; and

removing the sacrificial layer and the silicon-containing layer.

16. A method of forming a structure in a semiconductor device, the method comprising:

depositing a high-k dielectric layer on a semiconductor substrate;

depositing on the high-k dielectric layer a capping layer;

performing an oxygen-free plasma treatment process on at least one surface of a process chamber;

exposing an exposed surface of the capping layer to a plasma-excited hydrogen species and a plasma-excited nitrogen species in the process chamber;

exposing the exposed surface to air; and

performing a thermal anneal process on the high-k dielectric layer and the capping layer for a particular time and at a particular temperature.

17. A method of forming a structure in a semiconductor device, the method comprising:

depositing a high-k dielectric layer on a semiconductor substrate;

depositing on the high-k dielectric layer a capping layer;

exposing an exposed surface of the capping layer to a plasma-excited hydrogen species and a plasma-excited nitrogen species;

exposing the exposed surface to air;

performing a thermal anneal process on the high-k dielectric layer and the capping layer for a particular time and at a particular temperature;

wherein

the plasma-excited hydrogen species comprises ammonia, and

the plasma-excited nitrogen species comprises nitrogen gas (N₂).

18. A method of forming a structure in a semiconductor device, the method comprising:

depositing a high-k dielectric layer on a semiconductor substrate;

depositing a capping layer on the high-k dielectric layer to form a portion of the structure, wherein the portion includes the capping layer and the high-k dielectric layer, and wherein the deposited capping layer has an exposed surface; and

exposing the exposed surface to a plasma-excited hydrogen species and a plasma-excited nitrogen species, wherein the plasma-excited hydrogen species comprises ammonia, and the plasma-excited nitrogen species comprises nitrogen gas (N₂).

19. The method of claim 18, wherein the capping layer comprises a metal selected from a group consisting of titanium, tantalum and tungsten.

20. The method of claim 18, wherein a substrate bias is applied to the semiconductor substrate while exposing the exposed surface.