Die

• US 10,510,677 B2
• Filed: 08/21/2018
• Issued: 12/17/2019
• Est. Priority Date: 01/02/2017
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsai, Yung-Teng, Lin, Hung-Chin, Sun, Chia-Chen, Wu, Chih-Yu, Chen, Jun-Ming, Hung, Chung-Chih, Chen, Sheng-Chieh
• Primary Examiner(s): Pham, Hoa Q
• Application Number:
  US16/108,071
• Publication Number:
  US 20180356348A1
• Time in Patent Office: 483 Days
• Field of Search: 356399-401, 257499, 257797, 257620, 438401, 438462
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00

Abstract

A semiconductor structure includes a wafer comprising a plurality of viewing fields defined thereon, a plurality of dies defined by a scribe line formed in each viewing field, a plurality of mark patterns formed in the scribe line, and a plurality of anchor pattern respectively formed in the review fields, the anchor patterns being different from the mark patterns.

Claims

1. A die, comprising:

mark patterns in three corners of the die and only an anchor pattern in one corner of the die, wherein the anchor pattern is different from the mark patterns.

2. The die according to claim 1, wherein the mark patterns comprise alignment mark patterns.

3. The die according to claim 1, wherein the anchor pattern and mark patterns comprise different shapes.

4. The die according to claim 1, wherein the anchor pattern comprises a plurality of sub-patterns arranged therein, and at least a programmed defect is formed in one of the sub-patterns.

5. The die according to claim 4, wherein the sub-patterns comprise semiconductor patterns, metal patterns, or insulating patterns.

6. The die according to claim 4, wherein the programmed defect comprises a gap defect, a short-end defect, or a bridge defect.