Molded chip combination

• US 10,510,721 B2
• Filed: 08/11/2017
• Issued: 12/17/2019
• Est. Priority Date: 08/11/2017
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Bhagavat, Milind S., Fu, Lei, Barber, Ivor, Leong, Chia-Ken, Agarwal, Rahul
• Primary Examiner(s): Huynh, Andy
• Application Number:
  US15/675,214
• Publication Number:
  US 20190051633A1
• Time in Patent Office: 858 Days
• Field of Search: 257702
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05172 Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05664 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05669 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/05672 Vanadium [V] as principal constituent
• CPC Class Codes: H01L 2224/05684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1148 : Permanent masks, i.e. masks left in the finished device, e.g. passivation layers
• CPC Class Codes: H01L 2224/12105 : Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/18 : High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 23/293 : Organic, e.g. plastic
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/15192 : Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Various molded chip combinations and methods of manufacturing the same are disclosed. In one aspect, a molded chip combination is provided that includes a first semiconductor chip that has a first PHY region, a second semiconductor chip that has a second PHY region, an interconnect chip interconnecting the first PHY region to the second PHY region, and a molding joining together the first semiconductor chip, the second semiconductor chip and the interconnect chip.

Claims

1. A molded chip combination, comprising:

a first semiconductor chip having a first PHY region;

a second semiconductor chip having a second PHY region;

an interconnect chip interconnecting the first PHY region to the second PHY region;

a first molding layer laterally joining together the first semiconductor chip and the second semiconductor chip;

a second molding layer at least partially encapsulating the interconnect chip; and

a polymer layer positioned between the first molding layer and the second molding layer.

2. The molded chip combination of claim 1, wherein the first semiconductor chip includes a first plurality of interconnects to connect to a circuit board when the molded chip combination is mounted on the circuit board and the second semiconductor chip includes a second plurality of interconnects to connect to the circuit board when the molded chip combination is mounted on the circuit board.

3. The molded chip combination of claim 2, wherein the first semiconductor chip includes a first non-PHY region connected to the first interconnects and the second semiconductor chip includes a second non-PHY region connected to the second interconnects.

4. The molded chip combination of claim 1, wherein the first semiconductor chip includes a first non-PHY region, the first semiconductor chip PHY region having a first group of conductor pads each having a first lateral dimension and the first semiconductor chip non-PHY region has a second group of conductor pads each having substantially the same first lateral dimension, the polymer layer having a plurality of openings aligned with the first group of conductor pads and a plurality of interconnected openings aligned with the second group of conductor pads, the polymer layer having a conductive pillar in each of the openings and interconnected conductive pillars in each of the interconnected openings.

5. The molded chip combination of claim 4, comprising another conductive pillar on the interconnected conductive pillars, the another conductive pillar having second lateral dimension larger than the first lateral dimension.

6. The molded chip combination of claim 1, comprising a circuit board and the molded chip combination mounted on the circuit board.

7. The molded chip combination of claim 1, wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.

8. A molded chip combination, comprising:

a first semiconductor chip having a first PHY region and a first non-PHY region;

a second semiconductor chip having a second PHY region and a second non-PHY region;

an interconnect chip interconnecting the first PHY region to the second PHY region;

a first molding layer laterally joining together the first semiconductor chip and the second semiconductor chip;

a second molding layer joined to the first molding layer and at least partially encapsulating the interconnect chip and the first molding layer; and

a polymer layer positioned between the first molding layer and the second molding layer.

9. The molded chip combination of claim 8, wherein the first semiconductor chip includes a first plurality of interconnects to connect to a circuit board when the molded chip combination is mounted on the circuit board and the second semiconductor chip includes a second plurality of interconnects to connect to the circuit board when the molded chip combination is mounted on the circuit board.

10. The molded chip combination of claim 9, wherein the first semiconductor chip first non-PHY region is connected to the first interconnects and the second semiconductor chip second non-PHY region is connected to the second interconnects.

11. The molded chip combination of claim 8, wherein the first semiconductor chip PHY region includes a first group of conductor pads each having a first lateral dimension and the first semiconductor chip non-PHY region includes a second group of conductor pads each having substantially the same first lateral dimension, the polymer layer having a plurality of openings aligned with the first group of conductor pads and a plurality of interconnected openings aligned with the second group of conductor pads, the polymer layer having a conductive pillar in each of the openings and interconnected conductive pillars in each of the interconnected openings, the first semiconductor chip non-PHY region including another conductive pillar on the interconnected conductive pillars, the another conductive pillar having second lateral dimension larger than the first lateral dimension.

12. The molded chip combination of claim 8, comprising a circuit board and the molded chip combination mounted on the circuit board.

13. The molded chip combination of claim 8, wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.

14. A method of manufacturing a molded chip combination, comprising:

interconnecting a first PHY region of a first semiconductor chip to a second PHY region of a second semiconductor chip with an interconnect chip; and

molding together the first semiconductor chip and the second semiconductor chip with a first molding layer;

at least partially encapsulating the interconnect chip with a second molding layer; and

applying a polymer layer between the first molding layer and the second molding layer.

15. The method of claim 14, comprising fabricating a first plurality of interconnects on the first semiconductor chip to connect to a circuit board when the molded chip combination is mounted on the circuit board and a second plurality of interconnects on the second semiconductor chip to connect to the circuit board when the molded chip combination is mounted on the circuit board.

16. The method of claim 15, wherein the first semiconductor chip includes a first non-PHY region connected to the first interconnects and the second semiconductor chip includes a second non-PHY region connected to the second interconnects.

17. The method of claim 14, wherein the first semiconductor chip includes a first non-PHY region, the method comprises fabricating a first group of conductor pads of the first semiconductor chip PHY region each having a first lateral dimension and a second group of conductor pads of the first semiconductor chip non-PHY region each having substantially the same first lateral dimension, providing the polymer layer with a plurality of openings aligned with the first group of conductor pads and a plurality of interconnected openings aligned with the second group of conductor pads, and fabricating a conductive pillar in each of the openings and interconnected conductive pillars in each of the interconnected openings.

18. The method of claim 17, comprising positioning another conductive pillar on the interconnected conductive pillars, the another conductive pillar having second lateral dimension larger than the first lateral dimension.

19. The method of claim 14, comprising mounting the molded chip combination on a circuit board.

20. The method of claim 14, wherein the first semiconductor chip comprises a processor and the second semiconductor chip comprises a memory chip.