Semiconductor memory device and manufacturing method thereof

• US 10,510,758 B2
• Filed: 10/04/2017
• Issued: 12/17/2019
• Est. Priority Date: 10/04/2017
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Ho, Yen-Ting, Lin, Sung-Bin
• Primary Examiner(s): Kebede, Brook
• Application Number:
  US15/725,275
• Publication Number:
  US 20190103405A1
• Time in Patent Office: 804 Days
• Field of Search: 438257-267, 257314-322
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.

Claims

1. A manufacturing method of a semiconductor memory device, comprising:

forming a gate structure on a semiconductor substrate, wherein the gate structure comprises;

a floating gate electrode;

a control gate electrode disposed on the floating gate electrode;

a first oxide layer disposed between the floating gate electrode and the semiconductor substrate; and

a second oxide layer disposed between the floating gate electrode and the control gate electrode;

forming an oxide spacer layer conformally on the gate structure and the semiconductor substrate;

forming a nitride spacer on the oxide spacer layer and on a sidewall of the gate structure; and

performing an oxidation process after the step of forming the nitride spacer, wherein a thickness of an edge portion of the first oxide layer is increased by the oxidation process, and a thickness of an edge portion of the second oxide layer before the oxidation process is equal to the thickness of the edge portion of the second oxide layer after the oxidation process, wherein the oxide spacer layer directly contacts a topmost surface of the control gate electrode during the oxidation process.

2. The manufacturing method of the semiconductor memory device according to claim 1, wherein the second oxide layer is covered by the nitride spacer in a horizontal direction during the oxidation process.

3. The manufacturing method of the semiconductor memory device according to claim 2, wherein the horizontal direction is orthogonal to a thickness direction of the semiconductor substrate.

4. The manufacturing method of the semiconductor memory device according to claim 1, wherein the thickness of the edge portion of the first oxide layer is larger than a thickness of a center portion of the first oxide layer after the oxidation process.

5. The manufacturing method of the semiconductor memory device according to claim 4, wherein the thickness of the edge portion of the first oxide layer ranges from 1.3 times the thickness of the center portion of the first oxide layer to 1.5 times the thickness of the center portion of the first oxide layer after the oxidation process.

6. The manufacturing method of the semiconductor memory device according to claim 1, wherein a thickness of the oxide spacer layer is larger than a thickness of the first oxide layer before the oxidation process.

7. The manufacturing method of the semiconductor memory device according to claim 1, wherein a thickness of an edge portion of the second oxide layer is substantially equal to a thickness of a center portion of the second oxide layer with a tolerance of ±

5% after the oxidation process.

8. The manufacturing method of the semiconductor memory device according to claim 1, wherein the gate structure further comprises:

a nitride layer disposed between the control gate electrode and the second oxide layer; and

a third oxide layer disposed between the nitride layer and the control gate electrode.

9. The manufacturing method of the semiconductor memory device according to claim 8, wherein the second oxide layer, the nitride layer, and the third oxide layer are covered by the nitride spacer in a horizontal direction during the oxidation process.

10. The manufacturing method of the semiconductor memory device according to claim 8, wherein a thickness of an edge portion of the third oxide layer is substantially equal to a thickness of a center portion of the third oxide layer with a tolerance of ±

5% after the oxidation process.

11. The manufacturing method of the semiconductor memory device according to claim 1, further comprising:

forming a spacer structure on the oxide spacer layer and on the sidewall of the gate structure after the oxidation process.

12. The manufacturing method of the semiconductor memory device according to claim 11, wherein the nitride spacer is removed after the oxidation process and before the step of forming the spacer structure.

13. The manufacturing method of the semiconductor memory device according to claim 1, wherein the floating gate electrode and the control gate electrode comprise polycrystalline silicon respectively.

14. A semiconductor memory device, comprising:

a semiconductor substrate; and

a gate structure disposed on the semiconductor substrate, wherein the gate structure comprises;

a floating gate electrode;

a control gate electrode disposed on the floating gate electrode;

a first oxide layer disposed between the floating gate electrode and the semiconductor substrate, wherein a thickness of an edge portion of the first oxide layer is larger than a thickness of a center portion of the first oxide layer;

a second oxide layer disposed between the floating gate electrode and the control gate electrode, wherein a thickness of an edge portion of the second oxide layer is substantially equal to a thickness of a center portion of the second oxide layer; and

a first oxide spacer disposed on a sidewall of the gate structure, wherein the center portion of the first oxide layer is curved and the thickness of the edge portion of the first oxide layer is substantially equal to a thickness of the first oxide spacer.

15. The semiconductor memory device according to claim 14, wherein the thickness of the edge portion of the second oxide layer is substantially equal to the thickness of the center portion of the second oxide layer with a tolerance of ±

5%.

16. The semiconductor memory device according to claim 14, wherein the thickness of the edge portion of the first oxide layer ranges from 1.3 times the thickness of the center portion of the first oxide layer to 1.5 times the thickness of the center portion of the first oxide layer.

17. The semiconductor memory device according to claim 14, wherein the gate structure further comprises:

a nitride layer disposed between the control gate electrode and the second oxide layer; and

a third oxide layer disposed between the nitride layer and the control gate electrode.

18. The semiconductor memory device according to claim 17, wherein a thickness of an edge portion of the third oxide layer is substantially equal to a thickness of a center portion of the third oxide layer with a tolerance of ±

5%.

19. The semiconductor memory device according to claim 14, further comprising:

a first nitride spacer disposed on the first oxide spacer;

a second oxide spacer disposed on the first nitride spacer, wherein the first oxide spacer comprises an L-shaped spacer in a cross-sectional view of the semiconductor memory device, and the second oxide spacer comprises an L-shaped spacer in the cross-sectional view of the semiconductor memory device; and

a second nitride spacer disposed on the second oxide spacer.

20. The semiconductor memory device according to claim 14, further comprising:

a second oxide spacer disposed on the first oxide spacer, wherein the second oxide spacer comprises an L-shaped spacer in a cross-sectional view of the semiconductor memory device; and

a second nitride spacer disposed on the second oxide spacer.

21. A semiconductor memory device, comprising:

a semiconductor substrate; and

a gate structure disposed on the semiconductor substrate, wherein the gate structure comprises;

a floating gate electrode;

a control gate electrode disposed on the floating gate electrode;

a first oxide layer disposed between the floating gate electrode and the semiconductor substrate, wherein a thickness of an edge portion of the first oxide layer is larger than a thickness of a center portion of the first oxide layer; and

a second oxide layer disposed between the floating gate electrode and the control gate electrode, wherein a thickness of an edge portion of the second oxide layer is substantially equal to a thickness of a center portion of the second oxide layer; and

an oxide spacer layer disposed on a sidewall of the gate structure, wherein a thickness of the oxide spacer layer is larger than the thickness of the center portion of the first oxide layer, wherein the center portion of the first oxide layer is curved and the thickness of the edge portion of the first oxide layer is substantially equal to the thickness of the oxide spacer layer.