Semiconductor device having resistance elements and fabrication method thereof

• US 10,510,824 B2
• Filed: 05/30/2018
• Issued: 12/17/2019
• Est. Priority Date: 02/19/2016
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Ema, Taiji, Misawa, Nobuhiro, Kumeno, Kazuyuki, Yasuda, Makoto
• Primary Examiner(s): Ahmed, Selim U
• Application Number:
  US15/992,645
• Publication Number:
  US 20180277618A1
• Time in Patent Office: 566 Days
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/0802 Resistors only
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A semiconductor device includes as a resistance element a first polycrystalline silicon and a second polycrystalline silicon containing impurities, such as boron, of the same kind and having different widths. The first polycrystalline silicon contains the impurities at a concentration C_X. The second polycrystalline silicon has a width larger than a width of the first polycrystalline silicon and contains the impurities of the same kind at a concentration C_Y lower than the concentration C_X. A sign of a temperature coefficient of resistance (TCR) of the first polycrystalline silicon changes at the concentration C_X. A sign of a TCR of the second polycrystalline silicon changes at the concentration C_Y.

Claims

1. A semiconductor device comprising:

a first polycrystalline silicon having a negative temperature coefficient and having a first width; and

a second polycrystalline silicon having a positive temperature coefficient and having a second width larger than the first width, wherein;

the first polycrystalline silicon contains first impurities at a first concentration throughout a direction perpendicular to a direction of the first width, in a plan view; and

the second polycrystalline silicon contains the first impurities at the first concentration throughout a direction perpendicular to a direction of the second width, in the plan view.

2. The semiconductor device according to claim 1, wherein the first concentration and the second concentration are higher than or equal to 1×

10²⁰ cm<sup>−

3</sup> and lower than or equal to 1×

10²¹ cm<sup>−

3</sup>.

3. The semiconductor device according to claim 1, wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in series.

4. The semiconductor device according to claim 1, wherein the first impurities are p-type impurities.

5. The semiconductor device according to claim 1, wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in parallel.

6. The semiconductor device according to claim 1, wherein one end portion of the first polycrystalline silicon and one end portion of the second polycrystalline silicon are electrically connected in series.

7. The semiconductor device according to claim 1, wherein:

one end portion of the first polycrystalline silicon and one end portion of the second polycrystalline silicon are electrically connected;

the other end portion of the first polycrystalline silicon and the other end portion of the second polycrystalline silicon are electrically connected; and

the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in parallel.

8. The semiconductor device according to claim 1, wherein the first polycrystalline silicon and the second polycrystalline silicon are formed as continuous one body and electrically connected.

9. The semiconductor device according to claim 8, wherein the first polycrystalline silicon and the second polycrystalline silicon are electrically connected in series.

10. The semiconductor device according to claim 1, wherein a first sheet resistance of the first polycrystalline silicon is higher than a second sheet resistance of the second polycrystalline silicon.