Gate trench device with oxygen inserted si-layers

• US 10,510,836 B1
• Filed: 08/08/2018
• Issued: 12/17/2019
• Est. Priority Date: 08/08/2018
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Haase, Robert, Poelzl, Martin, Roesch, Maximilian, Leomant, Sylvain, Meiser, Andreas
• Primary Examiner(s): Vu, Hung K
• Application Number:
  US16/058,544
• Time in Patent Office: 496 Days
• Field of Search: None
• CPC Class Codes: H01L 21/2253 by ion implantation
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0865 Disposition
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a gate trench extending into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate. The semiconductor device further includes a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure extending along at least part of the channel region and disposed between the channel region and the highly doped body contact region. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si.

Claims

1. A semiconductor device, comprising:

a gate trench extending into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate;

a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench;

a source region in the Si substrate above the body region;

a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench; and

a diffusion barrier structure extending along at least part of the channel region and disposed between the channel region and the highly doped body contact region, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si.

2. The semiconductor device of claim 1, wherein the channel region, the gate electrode and the gate dielectric extend deeper into the Si substrate than the diffusion barrier structure.

3. The semiconductor device of claim 1, wherein the gate trench further includes a field electrode disposed below the gate electrode and a field dielectric separating the field electrode from the gate electrode and the Si substrate, and wherein the diffusion barrier structure terminates before reaching the field dielectric to provide a charge carrier pathway from the channel region to a drift zone below the body region without traversing the diffusion barrier structure.

4. The semiconductor device of claim 1, wherein the diffusion barrier structure extends over an upper side of the body region and is between the source region and the body region at the upper side of the body region.

5. The semiconductor device of claim 1, further comprising a capping layer of epitaxial Si interposed between the diffusion barrier structure and the gate dielectric, wherein the capping layer of epitaxial Si is doped to form the channel region.

6. The semiconductor device of claim 1, wherein the Si substrate comprises one or more Si epitaxial layers grown on a base Si substrate.

7. A method of manufacturing a semiconductor device, the method comprising:

forming a gate trench which extends into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate;

forming a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench;

forming a source region in the Si substrate above the body region;

forming a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench; and

forming a diffusion barrier structure which extends along at least part of the channel region and is disposed between the channel region and the highly doped body contact region, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si.

8. The method of claim 7, wherein forming the diffusion barrier structure comprises:

after etching the gate trench into the Si substrate and before forming the gate electrode and the gate dielectric in the gate trench, epitaxially growing the alternating layers of Si and oxygen-doped Si on the sidewall of the gate trench.

9. The method of claim 8, further comprising:

epitaxially growing the alternating layers of Si and oxygen-doped Si on a main surface of the Si substrate into which the gate trench is etched.

10. The method of claim 9, wherein the alternating layers of Si and oxygen-doped Si are epitaxially grown on the main surface of the Si substrate at the same time as on the sidewall of the gate trench.

11. The method of claim 9, wherein forming the contact trench comprises:

etching the contact trench through the alternating layers of Si and oxygen-doped Si epitaxially grown on the main surface of the Si substrate, through the source region, and into the body region;

implanting dopants into the bottom of the contact trench and annealing the dopants to form the highly doped body contact region at the bottom of the contact trench; and

filling the contact trench with the electrically conductive material which contacts the source region and the highly doped body contact region.

12. The method of claim 8, further comprising:

forming a capping layer of epitaxial Si between the diffusion barrier and the sidewall of the gate trench.

13. The method of claim 12, further comprising:

doping the capping layer to form the channel region.

14. The method of claim 8, further comprising:

after etching the gate trench into the Si substrate and before epitaxially growing the alternating layers of Si and oxygen-doped Si, forming a field electrode and a field dielectric separating the field electrode from the Si substrate in a lower part of the gate trench; and

after epitaxially growing the alternating layers of Si and oxygen-doped Si on the sidewall of the gate trench, recessing the field dielectric to expose a section of the trench sidewall which is uncovered by the diffusion barrier structure and to form a vertical gap between the field dielectric and the alternating layers of Si and oxygen-doped Si.

15. The method of claim 14, further comprising:

epitaxially growing a capping layer of epitaxial Si on the alternating layers of Si and oxygen-doped Si and on the exposed section of the trench sidewall uncovered by the diffusion barrier structure, the capping layer of epitaxial Si filling the vertical gap between the field dielectric and the alternating layers of Si and oxygen-doped Si and forming the channel region.

16. The method of claim 15, further comprising:

forming the gate dielectric on the capping layer of epitaxial Si.

17. The method of claim 16, further comprising:

implanting dopants through the gate dielectric and into a part of the capping layer of epitaxial Si epitaxially grown on the alternating layers of Si and oxygen-doped Si, to adjust a threshold voltage of the semiconductor device.

18. The method of claim 16, further comprising:

after forming the gate dielectric, filling the gate trench above the field electrode with an electrically conductive material that forms the gate electrode.

19. The method of claim 7, wherein forming the body region and the source region comprises:

after forming the diffusion barrier structure, implanting dopants of the opposite conductivity type into a main surface of the Si substrate into which the gate trench is etched.

20. The method of claim 7, wherein the Si substrate comprises one or more Si epitaxial layers grown on a base Si substrate.