Semiconductor devices with graded dopant regions

• US 10,510,842 B2
• Filed: 05/09/2017
• Issued: 12/17/2019
• Est. Priority Date: 09/03/2004
• Status: Active Grant

• Current Assignee: Greenthread, LLC
• Original Assignee: Greenthread, LLC
• Inventors: Rao, G.R. Mohan
• Primary Examiner(s): Arora, Ajay
• Application Number:
  US15/590,282
• Publication Number:
  US 20170243876A1
• Time in Patent Office: 952 Days
• Field of Search: 257655
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOFSFET and IGBT ICs, improvement in refresh time for DRAMs, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFETs, and a host of other applications.

Claims

1. A semiconductor device, comprising:

a substrate of a first doping type at a first doping level having first and second surfaces;

a first active region disposed adjacent the first surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed;

a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed;

transistors formed in at least one of the first active region or second active region; and

at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the first surface to the second surface of the substrate.

2. The semiconductor device of claim 1, wherein the substrate is a p-type substrate.

3. The semiconductor device of claim 1, wherein the substrate is an n-type substrate.

4. The semiconductor device of claim 1, wherein the substrate has epitaxial silicon on top of a nonepitaxial substrate.

5. The semiconductor device of claim 1, wherein the first active region and second active region contain one of either p-channel and n-channel devices.

6. The semiconductor device of claim 1, wherein the first active region and second active region contain either p-channel or n-channel devices in n-wells or p-wells, respectively, and each well has a graded dopant.

7. The semiconductor device of claim 1, wherein the first active region and second active region are each separated by at least one isolation region.

8. The semiconductor device of claim 1, wherein the graded dopant is fabricated with an ion implantation process.

17. The semiconductor device of claim 1, wherein the first and second active regions are formed adjacent the first surface of the substrate.

18. The semiconductor device of claim 1, wherein the transistors which can be formed in the first and second active regions are CMOS transistors requiring a source, a drain, a gate and a channel region.

9. A semiconductor device, comprising:

a substrate of a first doping type at a first doping level having first and second surfaces;

a first active region disposed adjacent the first surface of the substrate with a second doping type opposite in conductivity to the first doping type and within which transistors can be formed in the surface thereof;

a second active region separate from the first active region disposed adjacent to the first active region and within which transistors can be formed in the surface thereof;

transistors formed in at least one of the first active region or second active region; and

at least a portion of at least one of the first and second active regions having at least one graded dopant concentration to aid carrier movement from the surface to the substrate.

10. The semiconductor device of claim 9, wherein the substrate is a p-type substrate.

11. The semiconductor device of claim 9, wherein the substrate is an n-type substrate.

12. The semiconductor device of claim 9, wherein the substrate has epitaxial silicon on top of a nonepitaxial substrate.

13. The semiconductor device of claim 9, wherein the first active region and second active region contain at least one of either p-channel and n-channel devices.

14. The semiconductor device of claim 9, wherein the first active region and second active region contain either p-channel or n-channel devices in n-wells or p-wells, respectively, and each well has a graded dopant.

15. The semiconductor device of claim 9, wherein the first active region and second active region are each separated by at least one isolation region.

16. The semiconductor device of claim 9, wherein the graded dopant is fabricated with an ion implantation process.