Semiconductor devices and methods for forming the same

• US 10,510,878 B1
• Filed: 06/13/2018
• Issued: 12/17/2019
• Est. Priority Date: 06/13/2018
• Status: Active Grant

• Current Assignee: Vanguard International Semiconductor Corporation
• Original Assignee: Vanguard International Semiconductor Corporation
• Inventors: Chien, Chung-Yen, Fu, Sheng-Wei, Lee, Chung-Yeh
• Primary Examiner(s): Tobergte, Nicholas J
• Application Number:
  US16/007,169
• Publication Number:
  US 20190386132A1
• Time in Patent Office: 552 Days
• CPC Class Codes: H01L 21/28035 the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities H01L21/28105 takes precedence
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a semiconductor device is provided. A plurality of trenches are formed in the substrate. An isolation oxide layer is formed in the trenches and on the substrate. A shield polysilicon is deposited in the trenches and on the isolation oxide layer on the substrate. A first etching process is performed to remove a first portion of the shield polysilicon. A first removal process is performed to remove a first portion of the isolation oxide layer. A second etching process is performed to remove a second portion of the shield polysilicon. A second removal process is performed to remove a second portion of the isolation oxide layer. An inter-poly oxide layer is formed on the remaining shield polysilicon and the remaining isolation oxide layer, wherein the inter-poly oxide layer has a concave top surface.

Claims

1. A semiconductor device, comprising:

a substrate, comprising trenches;

an isolation oxide layer, disposed in the trenches;

a shield polysilicon, disposed in the trenches and partially surrounded by the isolation oxide layer; and

an inter-poly oxide layer, disposed on the isolation oxide layer and on the shield polysilicon;

wherein the inter-poly oxide layer has a concave top surface; and

a first top surface portion of the isolation oxide layer adjacent to the sidewall of the shield polysilicon has a first curvature, and a second top surface portion of the isolation oxide layer adjacent to a sidewall of one of the trenches has a second curvature, wherein the first curvature is greater than the second curvature.

2. The semiconductor device as claimed in claim 1, further comprising:

a gate oxide layer, disposed on the inter-poly oxide layer; and

a gate polysilicon, disposed on the gate oxide layer.

3. The semiconductor device as claimed in claim 1, wherein the inter-poly oxide layer completely covers the isolation oxide layer and the shield polysilicon.

4. The semiconductor device as claimed in claim 1, wherein a top surface of the isolation oxide layer extends upward from the sidewall of the shield polysilicon towards the sidewall of the one of the trenches.

5. The semiconductor device as claimed in claim 1, wherein a top surface of the isolation oxide layer has two different curvatures.

6. The semiconductor device as claimed in claim 1, wherein the profile of the concave top surface of the inter-poly oxide layer is substantially the same as the profile formed by the top surface of the isolation oxide layer and the top surface of the shield polysilicon.

7. The semiconductor device as claimed in claim 1, wherein a height difference between a first top surface portion of the isolation oxide layer adjacent to the shield polysilicon and a top surface of the shield polysilicon is less than 50 nm.

8. The semiconductor device as claimed in claim 1, wherein the height difference between the highest point of a second top surface portion of the isolation oxide layer adjacent to the one of the trenches and the lowest point of the first top surface portion of the isolation oxide layer adjacent to the shield polysilicon is between 30 nm and 40 nm and/or the average thickness of the inter-poly oxide layer is between 90 nm and 170 nm.

9. The semiconductor device as claimed in claim 1, wherein the angle between the concave top surface of the inter-poly oxide layer and the sidewall of the one of the trenches is between 110□

and 120□ and

/or the curvature of the concave top surface of the inter-poly oxide layer is between 0.045 and 0.055 nm<sup>−

1</sup>.

10. A method for forming the semiconductor device of claim 1, comprising:

providing a substrate;

forming trenches in the substrate;

forming an isolation oxide layer in the trenches and on the substrate;

depositing a shield polysilicon in the trenches and on the isolation oxide layer on the substrate;

performing a first etching process to remove a first portion of the shield polysilicon and expose a portion of the surface of the isolation oxide layer in the trenches;

performing a first removal process to remove a first portion of the isolation oxide layer;

performing a second etching process to remove a second portion of the shield polysilicon and expose another portion of the surface of the isolation oxide layer in the trenches;

performing a second removal process to remove a second portion of the isolation oxide layer; and

forming an inter-poly oxide layer on the remaining shield polysilicon and the remaining isolation oxide layer;

wherein the inter-poly oxide layer has a concave top surface.

11. The method for forming the semiconductor device as claimed in claim 10, further comprising:

forming a gate oxide layer on the inter-poly oxide layer; and

forming a gate polysilicon on the gate oxide layer.

12. The method for forming the semiconductor device as claimed in claim 10, wherein forming the inter-poly oxide layer on the remaining shield polysilicon and the remaining isolation oxide layer comprises:

depositing an inter-poly oxide in the trenches and over the substrate; and

performing a third etching process to remove a portion of the inter-poly oxide and expose a portion of the sidewall of the trenches.

13. The method for forming the semiconductor device as claimed in claim 12, wherein the inter-poly oxide completely covers the isolation oxide layer and the shield polysilicon.

14. The method for forming the semiconductor device as claimed in claim 10, further comprising:

before performing the first etching process to remove the first portion of the shield polysilicon, performing a chemical mechanical planarization polishing (CMP) process to the shield polysilicon until the isolation oxide layer is exposed.

15. The method for forming the semiconductor device as claimed in claim 10, wherein after performing the second etching process to remove the second portion of the shield polysilicon, a top surface of the remaining isolation oxide layer extends upward from the sidewall of the shield polysilicon towards the sidewall of one of the trenches.

16. The method for forming the semiconductor device as claimed in claim 10, wherein after performing the second etching process to remove the second portion of the shield polysilicon, the first top surface portion of the remaining isolation oxide layer adjacent to the sidewall of the shield polysilicon has a first curvature, and the second top surface portion of the remaining isolation oxide layer adjacent to the sidewall of one of the trenches has a second curvature, wherein the first curvature is greater than the second curvature.

17. The method for forming the semiconductor device as claimed in claim 10, wherein the profile of the concave top surface of the inter-poly oxide layer is substantially the same as the profile formed by the top surface of the remaining isolation oxide layer and the top surface of the remaining shield polysilicon.

18. The method for forming the semiconductor device as claimed in claim 10, wherein the height difference between the lowest point of a first top surface portion of the remaining isolation oxide layer adjacent to the shield polysilicon and a top surface of the remaining shield polysilicon is less than a thickness of the isolation oxide layer on the substrate.

19. The method for forming the semiconductor device as claimed in claim 10, wherein the angle between the concave top surface of the inter-poly oxide layer and the sidewall of one of the trenches is between 110□

and 120□ and

/or the curvature of the concave top surface of the inter-poly oxide layer is between 0.045 and 0.055 nm<sup>−

1</sup>.