Trench power MOSFET
First Claim
1. A method comprising:
- forming a trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type;
forming a conductive layer extending into the trench and on an edge of the trench;
forming a first dielectric layer on a bottom and sidewalls of the trench, wherein the first dielectric layer covers the conductive layer;
forming a field plate in the trench and over a bottom portion of the first dielectric layer;
forming a second dielectric layer over the field plate; and
forming a conductive region in the trench and over the second dielectric layer, wherein the conductive region is merged with the conductive layer to form a main gate.
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Abstract
A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.
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Citations
20 Claims
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1. A method comprising:
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forming a trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type; forming a conductive layer extending into the trench and on an edge of the trench; forming a first dielectric layer on a bottom and sidewalls of the trench, wherein the first dielectric layer covers the conductive layer; forming a field plate in the trench and over a bottom portion of the first dielectric layer; forming a second dielectric layer over the field plate; and forming a conductive region in the trench and over the second dielectric layer, wherein the conductive region is merged with the conductive layer to form a main gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method comprising:
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etching a semiconductor region to form a trench; forming a conductive layer in the trench and on a sidewall of the semiconductor region; forming a mask layer at a bottom of the trench; performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, with the tilt implantation performed using the mask layer as a first part of an implantation mask, and the conductive layer acting as a second part of the implantation mask; and forming a conductive region in the trench, wherein the conductive region is merged with the conductive layer. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A method comprising:
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etching a semiconductor region to form a trench; oxidizing a surface layer of the semiconductor region in the trench to form an oxide layer; forming a first conductive layer and a second conductive layer in the trench and on opposite sidewalls of the trench, wherein the first conductive layer has a bottom contacting a top surface of the oxide layer; etching the oxide layer and the semiconductor region to extend the trench deeper into the semiconductor region, with the first conductive layer and the second conductive layer acting as an etching mask so that the trench extends down between the first conductive layer and the second conductive layer; performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, with the tilt implantation performed using the first conductive layer and the second conductive layer as an implantation mask; and inserting a metallic region between and contacting the first conductive layer and the second conductive layer. - View Dependent Claims (17, 18, 19, 20)
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Specification