Trench power MOSFET

• US 10,510,880 B2
• Filed: 10/15/2018
• Issued: 12/17/2019
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Liu, Ruey-Hsin, Su, Po-Chih
• Primary Examiner(s): Bradley, Stephen M
• Application Number:
  US16/160,443
• Publication Number:
  US 20190051745A1
• Time in Patent Office: 428 Days
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Claims

1. A method comprising:

forming a trench in a semiconductor region, wherein the semiconductor region is of a first conductivity type;

forming a conductive layer extending into the trench and on an edge of the trench;

forming a first dielectric layer on a bottom and sidewalls of the trench, wherein the first dielectric layer covers the conductive layer;

forming a field plate in the trench and over a bottom portion of the first dielectric layer;

forming a second dielectric layer over the field plate; and

forming a conductive region in the trench and over the second dielectric layer, wherein the conductive region is merged with the conductive layer to form a main gate.

2. The method of claim 1 further comprising etching the semiconductor region to extend the trench deeper into the semiconductor region, with vertical portions of the conductive layer acting as an etching mask in the etching the semiconductor region.

3. The method of claim 1, wherein the forming the conductive layer comprises:

depositing a blanket conductive layer; and

removing portions of the blanket conductive layer outside of the trench.

4. The method of claim 1, wherein the forming the conductive layer comprises depositing a polysilicon layer.

5. The method of claim 1, wherein the forming the conductive layer comprises:

removing horizontal portions of the conductive layer; and

performing an implantation using vertical portions of the conductive layer as a part of an implantation mask to form a Doped Drain (DD) region in the semiconductor region.

6. The method of claim 5, wherein the implantation comprises a tilt implantation, and the DD region is overlapped by one of the vertical portions of the conductive layer.

7. The method of claim 5 further comprising forming a mask layer at the bottom of the trench, wherein a topmost end of the mask layer is lower than a bottom end of the conductive layer, with the implantation performed using the mask layer as a part of the implantation mask.

8. The method of claim 1, wherein the conductive region has edges flush with respective edges of the field plate.

9. The method of claim 1 further comprising implanting the semiconductor region to from a body region of a second conductivity type opposite to the first conductivity type, wherein the body region has a bottom lower than the main gate.

10. A method comprising:

etching a semiconductor region to form a trench;

forming a conductive layer in the trench and on a sidewall of the semiconductor region;

forming a mask layer at a bottom of the trench;

performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, with the tilt implantation performed using the mask layer as a first part of an implantation mask, and the conductive layer acting as a second part of the implantation mask; and

forming a conductive region in the trench, wherein the conductive region is merged with the conductive layer.

11. The method of claim 10 further comprising:

forming a field plate in the trench; and

forming a dielectric layer over the field plate, wherein the conductive region and the conductive layer are separated from the field plate by the dielectric layer.

12. The method of claim 10, wherein the DD region has a bottom higher than a bottom of the trench.

13. The method of claim 10, wherein the forming the conductive layer comprises depositing a polysilicon layer.

14. The method of claim 10, wherein the forming the conductive layer comprises:

depositing a blanket conductive layer comprising horizontal portions and vertical portions; and

etching the blanket conductive layer to remove the horizontal portions, wherein parts of the vertical portions in the trench remain as the conductive layer.

15. The method of claim 10, wherein the mask layer has a top surface lower than the conductive layer.

16. A method comprising:

etching a semiconductor region to form a trench;

oxidizing a surface layer of the semiconductor region in the trench to form an oxide layer;

forming a first conductive layer and a second conductive layer in the trench and on opposite sidewalls of the trench, wherein the first conductive layer has a bottom contacting a top surface of the oxide layer;

etching the oxide layer and the semiconductor region to extend the trench deeper into the semiconductor region, with the first conductive layer and the second conductive layer acting as an etching mask so that the trench extends down between the first conductive layer and the second conductive layer;

performing a tilt implantation to form a Doped Drain (DD) region in the semiconductor region, with the tilt implantation performed using the first conductive layer and the second conductive layer as an implantation mask; and

inserting a metallic region between and contacting the first conductive layer and the second conductive layer.

17. The method of claim 16, wherein the forming the first conductive layer and the second conductive layer comprises depositing a polysilicon layer.

18. The method of claim 16 further comprising forming a drain region overlapped by the DD region, wherein the drain region is electrically connected to the DD region.

19. The method of claim 16, wherein when the DD region has a bottom surface higher than a bottom of the trench.

20. The method of claim 16 further comprising:

forming a first dielectric layer on a bottom and sidewalls of the trench, with the first dielectric layer having an edge contacting an edge of the DD region;

forming a field plate in the trench and over a bottom portion of the first dielectric layer; and

forming a second dielectric layer over the field plate, wherein the metallic region is overlying and contacting the second dielectric layer.