Forming a sacrificial liner for dual channel devices

• US 10,510,892 B2
• Filed: 12/30/2016
• Issued: 12/17/2019
• Est. Priority Date: 09/26/2016
• Status: Active Grant

• Current Assignee: Tessera LLC (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Bu, Huiming, Cheng, Kangguo, Guo, Dechao, Kanakasabapathy, Sivananda K., Xu, Peng
• Primary Examiner(s): Nguyen, Cuong B
• Application Number:
  US15/395,637
• Publication Number:
  US 20180090604A1
• Time in Patent Office: 1,082 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Semiconductor devices include one or more fins. Each fin includes a top channel portion formed from a channel material and a bottom substrate portion formed from a same material as an underlying substrate, the top channel portion having a different width than the bottom substrate portion. An isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins. A space exists between at least a top portion of the isolation dielectric layer and the one or more fins. A gate dielectric is formed over the one or more fins and in the space.

Claims

1. A semiconductor device, comprising:

one or more fins, each fin comprising;

a top channel portion formed from a channel material;

a middle portion, and

a bottom substrate portion formed from a same material as an underlying substrate, each of the top channel portion and the middle portion having a different width than the bottom substrate portion;

an isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins;

an oxide layer formed between the bottom substrate portion of each fin and the isolation layer, wherein a space extending to a depth below the top surface of the middle portion and above a bottom end of the bottom substrate portion exists between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer; and

a gate dielectric, protruding into the space and in contact with the middle portion, formed over the one or more fins and comprising a portion formed from a material different from the oxide layer.

2. The semiconductor device of claim 1, comprising a plurality of such fins, wherein a first subset of the plurality of fins comprises a top channel portion formed from a first channel material and wherein a second subset of the plurality of fins comprises the top channel portion formed from a second channel material.

3. The semiconductor device of claim 2, wherein the first channel material is silicon and wherein the second channel material is silicon germanium.

4. The semiconductor device of claim 1, wherein the top channel portion of each of the one or more fins has a width that is greater than a width of the bottom substrate portion of each respective fin.

5. The semiconductor device of claim 4, wherein the middle portion is forming from a same material as the underlying substrate and having has a width that is greater than the width of the bottom substrate portion.

6. The semiconductor device of claim 1, wherein the oxide layer has a height lower than a bottom surface of the top channel portion of each fin.

7. The semiconductor device of claim 1, wherein the oxide layer has a height higher than a bottom surface of the top channel portion of each fin.

8. The semiconductor device of claim 2, wherein the channel semiconductor material is different from the substrate semiconductor material of each fin of each subset of the plurality of fins.

9. The semiconductor device of claim 1, wherein the gate dielectric is in direct contact with the middle portion.

10. The semiconductor device of claim 1, wherein the gate dielectric comes in physical contact with the middle portion along the fin sidewall.

11. A semiconductor device, comprising:

one or more fins, each fin comprising;

a top channel portion formed from a channel material;

a middle portion; and

a bottom substrate portion formed from a same material as an underlying substrate, wherein each of the top channel portion and the middle portion of each of the one or more fins has a width that is greater than a width of the bottom substrate portion of each respective fin;

an isolation dielectric layer formed between and around the bottom substrate portion of the one or more fins;

an oxide layer formed between the bottom substrate portion of each fin and the isolation layer, wherein a space extending to a depth below the top surface of the middle portion and above a bottom end of the bottom substrate portion exists between a sidewall of at least a top portion of the isolation dielectric layer and an adjacent sidewall of the one or more fins, above the oxide layer; and

a gate dielectric, protruding into the space and in contact with the middle portion, formed over the one or more fins and comprising a portion formed from a material different from the oxide layer.

12. The semiconductor device of claim 11, comprising a plurality of such fins, wherein a first subset of the plurality of fins comprises a top channel portion formed from a first channel material and wherein a second subset of the plurality of fins comprises the top channel portion formed from a second channel material.

13. The semiconductor device of claim 12, wherein the first channel material is silicon and wherein the second channel material is silicon germanium.

14. The semiconductor device of claim 11, wherein the middle portion is formed from a same material as the underlying substrate.

15. The semiconductor device of claim 11, wherein the gate dielectric is in physical contact with the middle portion.

16. The semiconductor device of claim 15, wherein the gate dielectric comes in direct contact with the middle portion along the fin sidewall.