Thin film transistor and manufacturing method therefor

• US 10,510,898 B2
• Filed: 03/15/2017
• Issued: 12/17/2019
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Industry-University Cooperation Foundation Hanyang University
• Original Assignee: Industry-University Cooperation Foundation Hanyang University
• Inventors: Park, Jin-Seong, Ok, Kyungchul, Jeong, Hyunjun
• Primary Examiner(s): Maruf, Sheikh
• Application Number:
  US15/459,699
• Publication Number:
  US 20170186877A1
• Time in Patent Office: 1,007 Days
• Field of Search: 257 43
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A thin film transistor is provided. The thin film transistor includes a substrate, an active pattern disposed on the substrate and including a nitride, a protective pattern disposed on the active pattern and including a non-nitride, a gate electrode overlapping with the active pattern, and a gate insulating layer between the gate electrode and the active pattern.

Claims

1. A thin film transistor comprising:

a substrate;

an active pattern, formed of ZnON, disposed on the substrate;

a protective pattern, formed of ZnO, directly disposed on the active pattern;

a gate electrode overlapping with the active pattern; and

a gate insulating layer, at least one portion of the gate insulating layer in a length direction being disposed between the gate electrode and the active pattern,

wherein the active pattern includes a channel therein.

2. The thin film transistor of claim 1, wherein the protective pattern is formed of a semiconductive non-nitride, and

wherein the active pattern has a higher mobility than the protective pattern.

3. The thin film transistor of claim 1, further comprising:

a passivation layer covering the protective pattern;

a source electrode penetrating the passivation layer so as to be in contact with a portion of the protective pattern adjacent to a side of the gate electrode; and

a drain electrode penetrating the passivation layer so as to be in contact with a portion of the protective pattern adjacent to another side of the gate electrode.

4. The thin film transistor of claim 1, further comprising:

a source electrode at a side of the gate electrode; and

a drain electrode at another side of the gate electrode,

wherein the source electrode and the drain electrode are in contact with portions of the protective pattern adjacent to the side and the another side of the gate electrode, respectively.

5. The thin film transistor of claim 1, wherein the active pattern is disposed between the protective pattern and the gate electrode.

6. The thin film transistor of claim 1, wherein the protective pattern is disposed between the active pattern and the gate electrode.

7. The thin film transistor of claim 1, wherein a thickness of the protective pattern is smaller than a thickness of the active pattern.

8. The thin film transistor of claim 1, wherein the protective pattern is in direct contact with the active pattern.