Loop filter initialization technique
First Claim
Patent Images
1. An apparatus comprising:
- an Nth-order loop filter having N integrators and an initialization path coupled between an input to the loop filter and an input to at least one of the N integrators; and
a control circuit configured to;
during a reset phase, cause an initialization voltage to be sampled into a capacitance of the initialization path; and
during an initialization phase immediately following the reset phase, cause the initialization voltage to be conveyed to the input of the at least one of the N integrators.
1 Assignment
0 Petitions
Accused Products
Abstract
An Nth-order loop filter includes N integrators (where N is an integer value). The loop filter includes an initialization path coupled between an input to the loop filter and an input of at least one of the integrators. A control circuit is coupled to the Nth order filter. During a reset phase, the control circuit causes an initialization voltage to be sampled into a capacitance of the initialization path. During an initialization phase immediately following the reset phase, the control circuit causes the initialization voltage to be conveyed to the input(s) of the at least one integrator.
10 Citations
20 Claims
-
1. An apparatus comprising:
-
an Nth-order loop filter having N integrators and an initialization path coupled between an input to the loop filter and an input to at least one of the N integrators; and a control circuit configured to; during a reset phase, cause an initialization voltage to be sampled into a capacitance of the initialization path; and during an initialization phase immediately following the reset phase, cause the initialization voltage to be conveyed to the input of the at least one of the N integrators. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 12, 13, 14)
-
-
9. A method comprising:
-
during a reset phase, resetting each of N integrators in an Nth order loop filer; sampling an initialization voltage into an initialization path of the Nth order loop filter during the reset phase; providing, during an initialization phase immediately following the reset phase, the initialization voltage to inputs of at least one of the N integrators the Nth order loop filter; and operating the loop filter in an integration phase subsequent to completion of the initialization phase. - View Dependent Claims (10, 11, 15, 16)
-
-
17. A system comprising:
-
a control circuit; and a sigma-delta analog-to-digital converter (ADC), the sigma-delta ADC including; a summing circuit configured to output a sum signal, the sum signal being a sum of an input signal and a feedback signal; a loop filter configured to output a filtered version of the sum signal, the loop filter including N integrators and an initialization path; and a quantizer configured to generate a binary code based on the filtered version of the sum signal; wherein the control circuit is configured to, during an initialization phase, cause state variables of the loop filter to be initialized with their respective steady state values, wherein initializing the loop filter includes providing an initialization voltage to an Nth integrator via the initialization path. - View Dependent Claims (18, 19, 20)
-
Specification