Baud rate tracking and compensation apparatus and method

• US 10,511,464 B2
• Filed: 09/12/2018
• Issued: 12/17/2019
• Est. Priority Date: 09/13/2017
• Status: Active Grant

• Current Assignee: Realtek Semiconductor Corp.
• Original Assignee: Realtek Semiconductor Corp.
• Inventors: Ye, Bixing, Peng, Zuohui, Li, Chaoming, Zhang, Qin, Wu, Zhilin
• Primary Examiner(s): Wolf, Darren E
• Application Number:
  US16/128,884
• Publication Number:
  US 20190081828A1
• Time in Patent Office: 461 Days
• Field of Search: None
• CPC Class Codes: H04B 10/40 Transceivers
• CPC Class Codes: H04B 10/50 Transmitters
• CPC Class Codes: H04B 10/60 Receivers
• CPC Class Codes: H04B 10/69 Electrical arrangements in the receiver
• CPC Class Codes: H04B 10/691 Arrangements for optimizing the photodetector in the receiver
• CPC Class Codes: H04B 10/695 Arrangements for optimizing the decision element in the receiver, e.g. by using automatic threshold control
• CPC Class Codes: H04L 25/0262 Arrangements for detecting the data rate of an incoming signal
• CPC Class Codes: H04L 25/493 by transition coding, i.e. the time-position or direction of a transition being encoded before transmission
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04L 7/044 using a single bit, e.g. start stop bit

Abstract

Disclosed is a baud rate tracking and compensation apparatus comprising: a clock generating component generating a clock; a sampling circuit sampling a reception signal according to the clock and thereby generating a sampled result, and the sampling circuit generating a transition notification signal when the sampled result indicates a transition of the reception signal; a clock counting circuit counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal; a bit counting circuit counting bit(s) between the first transition and the second transition according to the clock and a bit cycle; and a calculation circuit dividing the number of the cycles by the number of the bit(s) to obtain a calculation value, and then updating the bit cycle according to the calculation value.

Claims

1. An apparatus comprising:

a sampling circuit configured to sample a reception signal according to a clock and generate a sampled result, the sampling circuit being configured to generate a transition notification signal when the sampled result indicates a transition of the reception signal;

a clock counting circuit configured to count cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal and to generate a number of the cycles of the clock between the first transition of the reception signal and the second transition of the reception signal;

a bit counting circuit configured to count bit(s) between the first transition and the second transition according to the clock and a bit cycle indicative of cycles of the clock per bit, so as to generate a number of the bit(s) between the first transition of the reception signal and the second transition of the reception signal; and

a divisional circuit configured to update the bit cycle with a calculation value obtained by dividing the number of the cycles of the clock by the number of the bit(s).

2. The apparatus of claim 1, wherein the clock counting circuit is further configured to generate at least one bit-number notification signal(s) according to the clock and the bit cycle, and the bit counting circuit is configured to count the bit(s) between the first transition and the second transition according to the at least one bit-number notification signal(s) in addition to the clock and the bit cycle.

3. The apparatus of claim 2, wherein the bit counting circuit includes:

a bit counting component configured to count adjacent-transition bit(s) between every two adjacent transitions of the reception signal according to the at least one bit-number notification signal(s) and the transition notification signal within a duration between the first transition and the second transition; and

a bit-number summing component configured to obtain a number of the adjacent-transition bit(s), and thereby generate the number of the bit(s) between the first transition and the second transition.

4. The apparatus of claim 1, wherein the clock counting circuit includes:

a clock counting component configured to count adjacent-transition cycles of the clock between every two adjacent transitions of the reception signal according to the clock and the transition notification signal within a duration between the first transition and the second transition; and

a clock-number summing component configured to obtain a number of the adjacent-transition cycles of the clock, and thereby generate the number of the cycles of the clock between the first transition and the second transition.

5. The apparatus of claim 4, wherein the clock counting component is further configured to generate at least one bit-number notification signal(s) according to the clock and the bit cycle, and the bit counting circuit is further configured to count the bit(s) between the first transition and the second transition according to the at least one bit-number notification signal(s) in addition to the clock and the bit cycle.

6. The apparatus of claim 4, wherein the clock counting component is reset every time the clock counting component finishes counting the adjacent-transition cycles of the clock, and the clock-number summing component is reset after generating the number of the cycles of the clock between the first transition and the second transition.

7. The apparatus of claim 1, wherein the bit counting circuit includes:

a bit counting component configured to count adjacent-transition bit(s) between every two adjacent transitions of the reception signal according to the clock, the bit cycle and the transition notification signal within a duration between the first transition and the second transition; and

a bit-number summing component configured to obtain a number of the adjacent-transition bit(s) and thereby generate the number of the bit(s) between the first transition and the second transition.

8. The apparatus of claim 7, wherein the bit counting component is reset every time the bit counting component finishes counting the adjacent-transition bit(s), and the bit-number summing component is reset after generating the number of the bit(s) between the first transition and the second transition.

9. The apparatus of claim 1, wherein the calculation circuit includes:

a division enabling component configured to compare a current number of bit(s) with a threshold, in which the current number of bit(s) is generated by the bit counting circuit, and when the current number of bit(s) reaches the threshold, the current number of bit(s) is treated as the number of the bit(s) between the first transition and the second transition; and

a dividing component configured to be enabled by the division enabling component when the current number of bit(s) reaches the threshold, and the dividing component configured to divide the number of the cycles by the number of the bit(s) to obtain the calculation value.

10. The apparatus of claim 1, further comprising:

a bit-cycle storage component configured to store the bit cycle; and

a sampled-result storage component configured to store the sampled result.

11. The apparatus of claim 1, wherein the clock counting circuit is reset after finishing counting the cycles of the clock, and the bit counting circuit is reset after finishing counting the bit(s).

12. The apparatus of claim 1, wherein the reception signal between the first transition and the second transition includes no training sequence dedicated to baud rate tracking and/or calibration.

13. A method comprising:

generating a clock;

sampling a reception signal according to the clock and generating a sampled result;

generating a transition notification signal when the sampled result indicates a transition of the reception signal;

counting cycles of the clock between a first transition of the reception signal and a second transition of the reception signal according to the clock and the transition notification signal and generating a number of the cycles of the clock between the first transition and the second transition;

counting bit(s) between the first transition and the second transition according to the clock and a bit cycle indicative of cycles of the clock per bit and thereby generating a number of the bit(s) between the first transition and the second transition; and

updating the bit cycle with a calculation value obtained by dividing the number of the cycles of the clock by the number of the bit(s).

14. The method of claim 13, wherein the step of generating the number of the cycles includes:

counting adjacent-transition cycles of the clock between every two adjacent transitions of the reception signal according to the clock and the transition notification signal within a duration between the first transition and the second transition; and

executing a summing process to obtain of the number of the adjacent-transition cycles of the clock, and thereby generating the number of the cycles between the first transition and the second transition.

15. The method of claim 13, wherein the step of generating the number of the bit(s) includes:

counting adjacent-transition bit(s) between every two adjacent transitions of the reception signal according to the clock, the bit cycle and the transition notification signal within a duration between the first transition and the second transition; and

executing a summing process to obtain a number of the adjacent-transition bit(s), and thereby generating the number of the bit(s) between the first transition and the second transition.

16. The method of claim 13, wherein the step of obtaining the calculating value includes:

counting a current number of bit(s) according to the clock and the bit cycle within a duration between the first transition and the second transition;

comparing the current number of bit(s) with a threshold, in which when the current number of bit(s) reaches the threshold, the current number of bit(s) is treated as the number of bit(s) between the first transition and the second transition; and

when the current number of bit(s) reaches the threshold, dividing the number of the cycles by the number of the bit(s) to obtain the calculation value.

17. The method of claim 13, further comprising:

detecting a start bit of the reception signal, and when the start bit is detected, treating an initial transition of the start bit as the first transition.

18. The method of claim 13, further comprising:

before generating the sampled result, having a baud rate of an apparatus be the same as a baud rate of a transmitter, in which the reception signal originates from the transmitter.

19. The method of claim 13, wherein the reception signal between the first transition and the second transition includes no training sequence dedicated to baud rate tracking and/or calibration.