Pseudo main memory system

• US 10,515,006 B2
• Filed: 07/28/2017
• Issued: 12/24/2019
• Est. Priority Date: 07/29/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Malladi, Krishna T., Gim, Jongmin, Zheng, Hongzhong
• Primary Examiner(s): Bertram, Ryan
• Assistant Examiner(s): Kwong, Edmund H
• Application Number:
  US15/663,619
• Publication Number:
  US 20180032430A1
• Time in Patent Office: 879 Days
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/251 Local memory within processor subsystem

Abstract

A pseudo main memory system. The system includes a memory adapter circuit for performing memory augmentation using compression, deduplication, and/or error correction. The memory adapter circuit is connected to a memory, and employs the memory augmentation methods to increase the effective storage capacity of the memory. The memory adapter circuit is also connected to a memory bus and implements an NVDIMM-F or modified NVDIMM-F interface for connecting to the memory bus.

Claims

1. A computing system, comprising:

a central processing unit;

a memory system comprising;

a memory adapter circuit; and

a first memory; and

a second memory connected to the central processing unit through a memory management circuit,

wherein the memory adapter circuit has a first memory interface connected to the central processing unit and a second memory interface connected to the first memory, the first memory interface being a double data rate synchronous dynamic random-access memory interface, and

wherein the memory adapter circuit is configured to store data in, and retrieve data from, the first memory, utilizing augmentation of a storage capacity of the first memory, the augmentation being configured to increase free memory of the first memory according to an augmentation ratio,

wherein the memory adapter circuit is further configured to estimate the augmentation ratio based on compression and/or deduplication of previous write operations, and

wherein the central processing unit is configured to maintain a page cache in the second memory,

wherein the central processing unit is configured to call a cleancache function for clean pages when evicting the clean pages from the page cache, the cleancache function being configured to store the clean pages;

in the first memory when sufficient space is available in the first memory; and

in persistent storage otherwise, and

wherein the central processing unit is further configured to assess whether sufficient space is available in the first memory based on an estimated augmentation ratio, the estimated augmentation ratio being a function of augmentation ratios for data stored in the first memory over a set interval of time.

2. The computing system of claim 1, wherein the augmentation comprises at least one of:

compression;

deduplication; and

error correction.

3. The computing system of claim 1, wherein the first memory interface is a second generation or higher generation double data rate synchronous dynamic random-access memory interface.

4. The computing system of claim 3, wherein the second memory interface is a second generation or higher generation double data rate synchronous dynamic random-access memory interface.

5. The computing system of claim 3, wherein the first memory interface is an NVDIMM-F interface, and the computing system is configured to operate the memory system as a block device.

6. The computing system of claim 1, wherein the central processing unit is connected to the memory adapter circuit through a memory management circuit.

7. The computing system of claim 1, wherein the first memory is a dynamic random-access memory and the second memory interface is a second generation or higher generation double data rate synchronous dynamic random-access memory interface.

8. The computing system of claim 1, wherein the memory adapter circuit is a single integrated circuit configured to perform:

compression;

deduplication; and

error correction.

9. The computing system of claim 1, wherein the second memory is connected to the memory management circuit through a third memory interface, the third memory interface being a second generation or higher generation double data rate synchronous dynamic random-access memory interface.

10. The computing system of claim 1, wherein the cleancache function is configured to assess whether sufficient space is available in the first memory based on the estimated augmentation ratio.

11. The computing system of claim 1, wherein the central processing unit is configured to maintain a user memory space in the second memory, and

the central processing unit is configured to call a frontswap function for dirty pages when evicting the dirty pages from the user memory space, the frontswap function being configured to store the dirty pages:

in the first memory when sufficient space is available in the first memory; and

in persistent storage otherwise.

12. The computing system of claim 11, wherein the frontswap function is configured to assess whether sufficient space is available in the first memory based on the estimated augmentation ratio.

13. The computing system of claim 1, wherein the central processing unit is configured to:

execute one or more applications, and

in response to an application of the one or more applications to a sysinfo function, return;

a value for a total available memory based on a size of the first memory and size of the second memory, and

a value for a total free memory based on an amount of the free memory in the first memory and an amount of free memory in the second memory.

14. The computing system of claim 13, wherein the value for the total free memory is a sum of

an amount of free memory in the second memory, and

a product of a minimum augmentation ratio and an amount of the free memory in the first memory, the minimum augmentation ratio being:

the function of augmentation ratios for data stored in the first memory over the set interval of time when the set interval of time has elapsed since system startup, and

2.0 otherwise.

15. A method for operating a computer system, the computer system comprising:

a central processing unit;

a memory system comprising;

a memory adapter circuit; and

a first memory; and

a second memory connected to the central processing unit through a memory management circuit,

the memory adapter circuit having-a first memory interface connected to the central processing unit and a second memory interface connected to the first memory,

the first memory interface being a double data rate synchronous dynamic random-access memory interface, and

the method comprising storing data in, and retrieving data from, the first memory, utilizing augmentation of a storage capacity of the first memory, the augmentation being configured to increase free memory of the first memory according to an augmentation ratio,

wherein the memory adapter circuit is configured to estimate the augmentation ratio based on compression and/or deduplication of previous write operations, and

wherein the central processing unit is configured to maintain a page cache in the second memory,

wherein the central processing unit is configured to call a cleancache function for clean pages when evicting the clean pages from the page cache, the cleancache function being configured to store the clean pages;

in the first memory when sufficient space is available in the first memory; and

in persistent storage otherwise, and

wherein the central processing unit is further configured to assess whether sufficient space is available in the first memory based on an estimated augmentation ratio, the estimated augmentation ratio being a function of augmentation ratios for data stored in the first memory over a set interval of time.

16. The method of claim 15, wherein the augmentation comprises at least one of:

compression;

deduplication; and

error correction.

17. The method of claim 15, comprising using the memory system as a block device operable with an NVDIMM-F protocol.

18. The method of claim 15, wherein the memory adapter circuit is a single integrated circuit configured to perform:

compression;

deduplication; and

error correction.

19. A computing system, comprising:

a central processing unit;

a memory system comprising;

a first memory; and

memory adapter means for storing data in, and retrieving data from, the first memory, utilizing augmentation of a storage capacity of the first memory, the augmentation being configured to increase free memory of the first memory according to an augmentation ratio, the memory adapter means being configured to estimate the augmentation ratio based on compression and/or deduplication of previous write operations,

the memory adapter means having a first memory interface connected to the central processing unit and a second memory interface connected to the first memory,

the first memory interface being an NVDIMM-F interface, and

the computing system being configured to operate the memory system as a block device,

wherein the computing system further comprises;

a second memory connected to the central processing unit through a memory management circuit,

wherein the central processing unit is configured to maintain a page cache in the second memory,

wherein the central processing unit is configured to call a cleancache function for clean pages when evicting the clean pages from the page cache, the cleancache function being configured to store the clean pages;

in the first memory when sufficient space is available in the first memory; and

in persistent storage otherwise, and

wherein the central processing unit is further configured to assess whether sufficient space is available in the first memory based on an estimated augmentation ratio, the estimated augmentation ratio being a function of augmentation ratios for data stored in the first memory over a set interval of time.