Performance based memory block usage

• US 10,515,008 B2
• Filed: 10/25/2017
• Issued: 12/24/2019
• Est. Priority Date: 10/25/2017
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Sehgal, Rohit, Yang, Nian Niles
• Primary Examiner(s): Tsui, Daniel D
• Application Number:
  US15/793,387
• Publication Number:
  US 20190121725A1
• Time in Patent Office: 790 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be placed into a single level cell (SLC) block pool and one or more multi-level cell (MLC) block pools based on measured performance characteristic(s). For example, blocks that have a better SLC performance may be placed into the SLC block pool. Blocks may be targeted for garbage collection based on one or more measured performance characteristics. For example, blocks within an SLC block pool may be targeted for garbage collection based on a performance ranking of the SLC blocks, blocks within an MLC block pool may be targeted for garbage collection based on a performance ranking of the MLC blocks. Thus, the better performing blocks may be used more frequently, thereby improving performance.

Claims

1. An apparatus, comprising:

a plurality of blocks of memory cells;

performance measurement logic configured to measure one or more performance characteristics of ones of the blocks, the performance measurement logic further configured to measure single bit per cell performance of the plurality of blocks of memory cells; and

block selection logic configured to select a block for use based on the measured one or more performance characteristics, the block selection logic further configured to select a block for single bit per cell use based on the measured single bit per cell performance of the respective blocks.

2. The apparatus of claim 1, wherein the block selection logic is further configured to select blocks for a single level cell (SLC) pool and to select blocks for a multi-level cell (MLC) pool based on the one or more measured performance characteristics.

3. The apparatus of claim 1, wherein the block selection logic is further configured to garbage collect blocks based on the one or more measured performance characteristics.

4. The apparatus of claim 3, wherein the block selection logic is further configured to:

select blocks within a single bit per cell (SLC) block pool for garbage collection based on a ranking of the SLC blocks based on the one or more measured performance characteristics; and

select blocks within a multi-bit per cell (MLC) block pool for garbage collection based on a ranking of the MLC blocks based on the one or more measured performance characteristics.

5. The apparatus of claim 1, wherein the one or more performance characteristics comprise one or more of programming time or fail bit count, wherein the block selection logic is further configured to select a block for use based on one or more of the measured programming time or the measured fail bit count for the respective blocks.

6. The apparatus of claim 1, wherein the one or more performance characteristics comprise programming time, wherein the block selection logic is configured to select a block for use based on the measured programming time for the respective blocks.

7. The apparatus of claim 1, wherein the one or more performance characteristics comprise fail bit count, wherein the block selection logic is further configured to select a block for use based on the measured fail bit count for the respective blocks.

8. The apparatus of claim 1, wherein:

the performance measurement logic is further configured to measure multi-bit per cell performance of blocks not selected for single bit per cell use; and

the block selection logic is further configured to select a block for multi-bit per cell use based on the measured multi-bit per cell performance of the respective blocks not selected for single bit per cell use.

9. The apparatus of claim 1, wherein:

the performance measurement logic is further configured to determine a metric based on one or more of single bit per cell programming time or fail bit count for memory cells programmed to a single bit per cell; and

the block selection logic is further configured to place blocks having the highest metric into a pool of SLC blocks and to place blocks having lower metrics into one or more pools of MLC blocks, wherein a higher metric is associated with better performance.

10. The apparatus of claim 9, wherein the metric is based on single bit per cell programming time.

11. The apparatus of claim 9, wherein the metric is based on single bit per cell programming time and fail bit count for memory cells programmed to a single bit per cell.

12. A method comprising:

determining, by a control circuit on a non-volatile storage device, one or more performance metrics for ones of a plurality of blocks of memory cells in the non-volatile storage device, the one or more performance metrics comprise a single bit per cell programming time metric;

ranking, by the control circuit, the plurality of blocks based on the one or more performance metrics, the ranking the plurality of blocks comprises ranking the blocks based on the single bit per cell programming time metric; and

selecting blocks for use, by the control circuit, based on the ranking, the selecting blocks for use comprises selecting blocks for single bit per cell use based on the single bit per cell programming time metric of the respective blocks.

13. The method of claim 12, wherein:

the ranking the plurality of blocks comprises ranking the blocks from fastest single bit per memory cell programming time to slowest single bit per memory cell programming time; and

the selecting blocks for use comprises placing the fastest blocks at single bit per memory cell programming time into a single level cell (SLC) block pool and blocks having the slowest single bit per memory cell programming time into one or more multi-level cell (MLC) block pools.

14. The method of claim 13, further comprising:

selecting blocks within the SLC block pool for garbage collection based on the ranking of the SLC blocks; and

selecting blocks within the one or more MLC block pools for garbage collection based on the ranking of the MLC blocks.

15. The method of claim 13, wherein ranking the plurality of blocks;

and placing blocks into the single level cell (SLC) block pool and the one or more multi-level cell (MLC) block pools comprises;

ranking blocks not placed into the SLC block pool in terms of two-bit per memory cell programming time; and

placing blocks fastest at two-bit per memory cell programming time in a pool for programming at two bits per memory cell; and

placing remaining blocks into a pool for programming at more than two bits per memory cell.

16. A non-volatile memory device, comprising:

a plurality of blocks of memory cells;

performance measurement means for measuring one or more performance characteristics of ones of the blocks of memory cells, the one or more performance characteristics comprise a single bit per cell fail bit count (FBC);

ranking means for ranking the plurality of blocks based on the one or more performance characteristics, the ranking the plurality of blocks comprises ranking the blocks based on the single bit per cell FBC; and

block selection means for selecting blocks for single level cell (SLC) use and for selecting blocks for multi-level cell (MLC) use based on the ranking, the block selection means further selecting blocks for single bit per cell use based on the single bit per cell FBC of the respective blocks.

17. The non-volatile memory device of claim 16, wherein the block selection means is further for:

placing blocks having the lowest single bit per cell FBC in a single level cell (SLC) block pool; and

placing blocks having a higher single bit per cell FBC in one or more multi-level cell (MLC) block pools.

18. The non-volatile memory device of claim 17, wherein the block selection means is further for:

selecting blocks within the SLC block pool for garbage collection based on the ranking of the SLC blocks; and

selecting blocks within the one or more MLC block pools for garbage collection based on the ranking of the MLC blocks.