Hamming-distance analyzer and method for analyzing hamming-distance

• US 10,515,713 B2
• Filed: 06/18/2018
• Issued: 12/24/2019
• Est. Priority Date: 11/28/2016
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lu, Shih-Lien Linus
• Primary Examiner(s): Nguyen, Thien
• Application Number:
  US16/011,215
• Publication Number:
  US 20180301204A1
• Time in Patent Office: 554 Days
• CPC Class Codes: G11C 2029/2602 Concurrent test
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/14 Implementation of control logic, e.g. test mode decoders
• CPC Class Codes: G11C 29/26 Accessing multiple arrays G11C29/24 takes precedence
• CPC Class Codes: G11C 29/38 Response verification devices
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/56008 Error analysis, representation of errors
• CPC Class Codes: G11C 29/56016 Apparatus features

Abstract

A device is disclosed for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The device includes a comparing circuit and a calculating circuit. The comparing circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operated in conditions that are different from each other, to generate a plurality of first comparing results. The calculating circuit is configured to output, according to the plurality of first comparing results, a maximum hamming distance between two of the first responses and the plurality of responses of the first memory circuit.

Claims

1. A device for testing a memory, wherein the memory comprises a first memory circuit and a second memory circuit, wherein the second memory circuit is configured to store a first response in a plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second response of a plurality of responses of the second memory circuit, wherein the device comprises:

a comparing circuit configured to compare the first response stored in the second memory circuit with the plurality of responses of the first memory circuit operated in operating conditions corresponding to different operating environments, to generate a plurality of first comparing results, and configured to compare the second response stored in the first memory circuit with the plurality of responses of the second memory circuit operated in conditions corresponding to the different operating environments, to generate a plurality of second comparing results,

wherein the comparing circuit is further configured to generate a final result according to the plurality of first comparing results and the plurality of second comparing results; and

a calculating circuit configured to output, according to the final result, a maximum hamming distance between two of the plurality of responses of the first memory circuit.

2. The device of claim 1, wherein the calculating circuit is configured to output, according to the final result, a maximum hamming distance between two of the plurality of responses of the second memory circuit.

3. The device of claim 2, further comprising:

a register configured to store the plurality of first comparing results, the plurality of second comparing results, and the final result, wherein the register comprises a first registering circuit and a second registering circuit, wherein the first registering circuit is configured to store the plurality of first comparing results for the calculation of the maximum hamming distance, and the second registering circuit is configured to store the plurality of second comparing results for the calculation of the maximum hamming distance.

4. The device of claim 2, wherein the comparing circuit comprises:

an exclusive OR gate configured to perform an exclusive OR operation of the first response and each one of the plurality of responses of the first memory circuit, and perform an exclusive OR operation of the second response and each one of the plurality of responses of the second memory circuit.

5. The device of claim 2, wherein the calculating circuit comprises:

a counter configured to generate a first value indicating a number of bits, in a corresponding comparing result of the plurality of first comparing results, having a same logic value, and generate a second value indicating a number of bits, in a corresponding comparing result of the plurality of second comparing results, having a same logic value.

6. The device of claim 5, wherein the calculating circuit is further configured to generate the maximum hamming distance according to the first value and a bit number of the corresponding comparing result of the plurality of first comparing results, and generate the maximum hamming distance according to the second value and a bit number of the corresponding comparing result of the plurality of second comparing results.

19. The device of claim 1, wherein

when an Xth bit of a comparing result, which is generated prior to a following comparing result of the first comparing results, of the first comparing results has a first logic value, an Xth bit of the following comparing result is adjusted to have the first logic value,

wherein each of the first comparing results has n bits, each of the plurality of responses has n bits, X and n are each a positive integer, and X is smaller than or equal to n.

20. The device of claim 19, wherein

when an Yth bit of the comparing result, which is generated prior to the following comparing result of the first comparing results, of the first comparing results has a second logic value different from the first logic value, and when an Yth bit of the first response is different from an Yth bit of a corresponding response of the plurality of responses of the first memory circuit, an Yth bit of the following comparing result is adjusted to have the second logic value,

wherein Y is a positive integer smaller than or equal to n.

7. A method, comprising:

retaining a first response in a plurality of responses of a first memory circuit of a memory in a first operating condition of operating conditions;

sequentially comparing the first response stored in a second memory circuit of the memory with the plurality of responses of the first memory circuit in the operating conditions corresponding to different operating environments, to generate a plurality of first comparing results, wherein each comparing result of the plurality of first comparing results is generated by adjusting a previous comparing result of the plurality of first comparing results;

retaining a second response of a plurality of responses of the second memory circuit of the memory in a second operating condition of the operating conditions;

sequentially comparing the second response stored in the first memory circuit of the memory with the plurality of responses of the second memory circuit in the operating conditions corresponding to the different operating environments, to generate a plurality of second comparing results, wherein each comparing result of the plurality of second comparing results is generated by adjusting a previous comparing result of the plurality of second comparing results;

generating a final result based on sequentially comparing the first response with the plurality of responses of the first memory circuit and sequentially comparing the second response with the plurality of response of the second memory circuit; and

obtaining, according to the final result, a maximum difference between two of the plurality of responses of the first memory circuit.

8. The method of claim 7, wherein retaining the first response of the first memory circuit comprises:

copying the first response into the second memory circuit of the memory; and

retaining the copied first response in the second memory circuit.

9. The method of claim 7, wherein retaining the first response comprises:

generating the first response by the second memory circuit.

10. The method of claim 9, wherein retaining the second response of the second memory circuit comprises:

copying the second response into the first memory circuit of the memory; and

retaining the copied second response in the first memory circuit.

11. The method of claim 10, wherein retaining the second response comprises:

generating the second response by the first memory circuit.

12. The method of claim 11, further comprising:

temporarily storing the plurality of first comparing results and the plurality of second comparing results for outputting a maximum hamming distance.

13. The method of claim 12, wherein obtaining the maximum difference comprises:

generating a first value indicating a number of bits, in a corresponding comparing result of the plurality of first comparing results, having a same logic value, and generating a second value indicating a number of bits, in a corresponding comparing result of the plurality of second comparing results, having a same logic value.

14. The method of claim 13, wherein outputting the maximum hamming distance further comprises:

generating the maximum hamming distance according to the first value and a bit number of the corresponding comparing result of the plurality of first comparing results, and generating the maximum hamming distance according to the second value and a bit number of the corresponding comparing result of the plurality of second comparing results.

15. The method of claim 14, wherein comparing the first response stored in the second memory circuit of the memory with the plurality of responses of the first memory circuit comprises:

performing an exclusive OR operation of the first response stored in the second memory circuit and each one of the plurality of responses of the first memory circuit.

16. The method of claim 15, wherein comparing the second response stored in the first memory circuit of the memory with the plurality of responses of the second memory circuit comprises:

performing an exclusive OR operation of the second response stored in the first memory circuit and each one of the plurality of responses of the second memory circuit.

17. A method, comprising:

operating a first memory circuit of a memory in operating conditions corresponding to different operating environments, to obtain a plurality of responses of the first memory circuit, and storing a first response of the plurality of responses of the first memory circuit in a second memory circuit of the memory;

performing an exclusive OR operation of the first response of the plurality of responses of the first memory circuit stored in the second memory circuit of the memory and other responses of the plurality of responses of the first memory circuit sequentially, to generate comparing results of the plurality of responses of the first memory circuit;

operating the second memory circuit in operating conditions corresponding to the different operating environments, to obtain a plurality of responses of the second memory circuit, and storing a second response of the plurality of responses of the second memory circuit in the first memory circuit;

performing an exclusive OR operation of the second response of the plurality of responses of the second memory circuit stored in the first memory circuit and other responses of the plurality of responses of the second memory circuit sequentially, to generate comparing results of the plurality of responses of the second memory circuit;

generating a final comparing result according to performing the exclusive OR operation of the first response of the plurality of responses of the first memory circuit and performing an exclusive OR operation of the second response of the plurality of responses of the second memory circuit; and

outputting, according to the final comparing result, a maximum hamming distance between two of the plurality of responses of the first memory circuit.

18. The method of claim 17, wherein outputting the maximum hamming distance comprises:

generating a value indicating a number of bits, in the final comparing result, having a same logic value; and

generating the maximum hamming distance according to the value and a bit number of the final comparing result.