Hamming-distance analyzer and method for analyzing hamming-distance
First Claim
1. A device for testing a memory, wherein the memory comprises a first memory circuit and a second memory circuit, wherein the second memory circuit is configured to store a first response in a plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second response of a plurality of responses of the second memory circuit, wherein the device comprises:
- a comparing circuit configured to compare the first response stored in the second memory circuit with the plurality of responses of the first memory circuit operated in operating conditions corresponding to different operating environments, to generate a plurality of first comparing results, and configured to compare the second response stored in the first memory circuit with the plurality of responses of the second memory circuit operated in conditions corresponding to the different operating environments, to generate a plurality of second comparing results,wherein the comparing circuit is further configured to generate a final result according to the plurality of first comparing results and the plurality of second comparing results; and
a calculating circuit configured to output, according to the final result, a maximum hamming distance between two of the plurality of responses of the first memory circuit.
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Accused Products
Abstract
A device is disclosed for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The device includes a comparing circuit and a calculating circuit. The comparing circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operated in conditions that are different from each other, to generate a plurality of first comparing results. The calculating circuit is configured to output, according to the plurality of first comparing results, a maximum hamming distance between two of the first responses and the plurality of responses of the first memory circuit.
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Citations
20 Claims
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1. A device for testing a memory, wherein the memory comprises a first memory circuit and a second memory circuit, wherein the second memory circuit is configured to store a first response in a plurality of responses of the first memory circuit, and the first memory circuit is configured to store a second response of a plurality of responses of the second memory circuit, wherein the device comprises:
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a comparing circuit configured to compare the first response stored in the second memory circuit with the plurality of responses of the first memory circuit operated in operating conditions corresponding to different operating environments, to generate a plurality of first comparing results, and configured to compare the second response stored in the first memory circuit with the plurality of responses of the second memory circuit operated in conditions corresponding to the different operating environments, to generate a plurality of second comparing results, wherein the comparing circuit is further configured to generate a final result according to the plurality of first comparing results and the plurality of second comparing results; and a calculating circuit configured to output, according to the final result, a maximum hamming distance between two of the plurality of responses of the first memory circuit. - View Dependent Claims (2, 3, 4, 5, 6, 19, 20)
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7. A method, comprising:
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retaining a first response in a plurality of responses of a first memory circuit of a memory in a first operating condition of operating conditions; sequentially comparing the first response stored in a second memory circuit of the memory with the plurality of responses of the first memory circuit in the operating conditions corresponding to different operating environments, to generate a plurality of first comparing results, wherein each comparing result of the plurality of first comparing results is generated by adjusting a previous comparing result of the plurality of first comparing results; retaining a second response of a plurality of responses of the second memory circuit of the memory in a second operating condition of the operating conditions; sequentially comparing the second response stored in the first memory circuit of the memory with the plurality of responses of the second memory circuit in the operating conditions corresponding to the different operating environments, to generate a plurality of second comparing results, wherein each comparing result of the plurality of second comparing results is generated by adjusting a previous comparing result of the plurality of second comparing results; generating a final result based on sequentially comparing the first response with the plurality of responses of the first memory circuit and sequentially comparing the second response with the plurality of response of the second memory circuit; and obtaining, according to the final result, a maximum difference between two of the plurality of responses of the first memory circuit. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method, comprising:
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operating a first memory circuit of a memory in operating conditions corresponding to different operating environments, to obtain a plurality of responses of the first memory circuit, and storing a first response of the plurality of responses of the first memory circuit in a second memory circuit of the memory; performing an exclusive OR operation of the first response of the plurality of responses of the first memory circuit stored in the second memory circuit of the memory and other responses of the plurality of responses of the first memory circuit sequentially, to generate comparing results of the plurality of responses of the first memory circuit; operating the second memory circuit in operating conditions corresponding to the different operating environments, to obtain a plurality of responses of the second memory circuit, and storing a second response of the plurality of responses of the second memory circuit in the first memory circuit; performing an exclusive OR operation of the second response of the plurality of responses of the second memory circuit stored in the first memory circuit and other responses of the plurality of responses of the second memory circuit sequentially, to generate comparing results of the plurality of responses of the second memory circuit; generating a final comparing result according to performing the exclusive OR operation of the first response of the plurality of responses of the first memory circuit and performing an exclusive OR operation of the second response of the plurality of responses of the second memory circuit; and outputting, according to the final comparing result, a maximum hamming distance between two of the plurality of responses of the first memory circuit. - View Dependent Claims (18)
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Specification